add demosaic testbench using verilator
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@ -89,7 +89,7 @@ run:
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@echo "-- RUN ---------------------"
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@rm -rf logs
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@mkdir -p logs
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obj_dir/Vtop +trace
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obj_dir/V$(TOP_MODULE) +trace
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@echo
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@echo "-- COVERAGE ----------------"
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@ -5,19 +5,53 @@
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#include <systemc>
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// Include common routines
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#include <sys/stat.h> // mkdir
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#include <verilated.h>
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#include <verilated_vcd_sc.h>
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#include <sys/stat.h> // mkdir
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// Include model header, generated from Verilating "top.v"
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// Include model header, generated from Verilating "demo.v"
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#include "Vdemosaic2.h"
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// Handle file
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#include <fstream>
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#include <iostream>
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#define IM_WIDTH 512
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#define IM_HEIGHT 256
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#define IM_SIZE (IM_WIDTH * IM_HEIGHT)
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using namespace std;
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using namespace sc_core;
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using namespace sc_dt;
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int sc_main(int argc, char* argv[]) {
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// This is a more complicated example, please also see the simpler examples/make_hello_c.
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// Open image
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ifstream in_image;
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ofstream out_image;
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in_image.open("./transform/test.bin", ios::in | ios::binary);
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out_image.open("./transform/out.bin", ios::out | ios::binary);
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if (!in_image.is_open()) {
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cout << "Open image fail" << endl;
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exit(0);
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} else {
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cout << "Ready to sim" << endl;
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}
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// Read image
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uint8_t buf[IM_SIZE * 2] = {0};
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in_image.read((char*)buf, IM_SIZE);
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in_image.close();
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// Reshape data
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uint16_t image[IM_HEIGHT][IM_WIDTH] = {0};
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uint32_t i = 0;
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for (int y = 0; y < IM_HEIGHT; y++) {
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for (int x = 0; x < IM_WIDTH; x++) {
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image[y][x] = (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
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}
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}
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// This is a more complicated example, please also see the simpler
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// examples/make_hello_c.
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// Create logs/ directory in case we have traces to put under it
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Verilated::mkdir("logs");
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@ -30,7 +64,8 @@ int sc_main(int argc, char* argv[]) {
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// May be overridden by commandArgs argument parsing
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Verilated::randReset(2);
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// Before any evaluation, need to know to calculate those signals only used for tracing
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// Before any evaluation, need to know to calculate those signals only used
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// for tracing
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Verilated::traceEverOn(true);
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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@ -45,17 +80,33 @@ int sc_main(int argc, char* argv[]) {
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// Define interconnect
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sc_signal<bool> reset;
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sc_signal<uint32_t> in_small;
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sc_signal<bool> in_en;
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sc_signal<bool> in_que;
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sc_signal<bool> in_line;
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sc_signal<uint32_t> data_in[3];
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sc_signal<bool> out_en;
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sc_signal<uint32_t> out_r, out_g, out_b;
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// Construct the Verilated model, from inside Vtop.h
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end
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const std::unique_ptr<Vdemosaic2> top{new Vdemosaic2{"top"}};
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at
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// end
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const std::unique_ptr<Vdemosaic2> demo{new Vdemosaic2{"demo"}};
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// Attach Vtop's signals to this upper model
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top->clk(clk);
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top->reset(reset);
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demo->clk(clk);
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demo->reset(reset);
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demo->data_en(in_en);
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demo->data_que(in_que);
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demo->data_line(in_line);
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demo->data_in[0](data_in[0]);
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demo->data_in[1](data_in[1]);
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demo->data_in[2](data_in[2]);
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demo->out_en(out_en);
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demo->out_r(out_r);
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demo->out_g(out_g);
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demo->out_b(out_b);
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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@ -68,22 +119,49 @@ int sc_main(int argc, char* argv[]) {
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if (flag && 0 == std::strcmp(flag, "+trace")) {
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std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
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tfp = new VerilatedVcdSc;
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top->trace(tfp, 99); // Trace 99 levels of hierarchy
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demo->trace(tfp, 99); // Trace 99 levels of hierarchy
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Verilated::mkdir("logs");
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tfp->open("logs/vlt_dump.vcd");
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}
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// Simulate until $finish
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uint16_t pos_x = 0, pos_y = 0;
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uint32_t out[IM_SIZE] = {0}, out_head = 0;
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while (!Verilated::gotFinish()) {
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// Flush the wave files each cycle so we can immediately see the output
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// Don't do this in "real" programs, do it in an abort() handler instead
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if (tfp) tfp->flush();
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// Apply inputs
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if (sc_time_stamp() > sc_time(1, SC_NS) && sc_time_stamp() < sc_time(10, SC_NS)) {
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reset_l = !1; // Assert reset
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if (sc_time_stamp() < sc_time(10, SC_NS)) {
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reset.write(1); // Assert reset
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} else {
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reset_l = !0; // Deassert reset
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reset.write(0); // Deassert reset
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}
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// Send image data and Read RGB image data
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if (sc_time_stamp() > sc_time(10, SC_NS) && clk.posedge()) {
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// Send image data to demosaic
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if (in_que.read() && pos_y < IM_HEIGHT) {
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in_en.write(1);
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data_in[0].write(image[pos_y + 0][pos_x++]);
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data_in[1].write(image[pos_y + 1][pos_x++]);
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data_in[2].write(image[pos_y + 2][pos_x++]);
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if (pos_x >= IM_WIDTH) {
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pos_x = 0;
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pos_y++;
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}
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} else {
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in_en.write(0);
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}
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// Read image data
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if (out_en.read()) {
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out[out_head++] = ((uint8_t)(out_r.read() * 5 / 12) << 10) +
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((uint8_t)(out_g.read() * 5 / 12) << 5) +
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((uint8_t)(out_b.read() * 5 / 12) << 0);
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}
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}
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// Simulate 1ns
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@ -91,7 +169,7 @@ int sc_main(int argc, char* argv[]) {
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}
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// Final model cleanup
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top->final();
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demo->final();
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// Close trace if opened
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if (tfp) {
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@ -104,6 +182,13 @@ int sc_main(int argc, char* argv[]) {
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Verilated::mkdir("logs");
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VerilatedCov::write("logs/coverage.dat");
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#endif
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// Save final output image
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for (uint32_t i = 0; i < IM_SIZE; i++) {
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buf[i * 2] = (out[i] & 0xffff0000) >> 16;
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buf[i * 2 + 1] = (out[i] & 0x0000ffff);
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}
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out_image.write((const char*)buf, 2 * IM_SIZE);
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out_image.close();
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// Return good completion status
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return 0;
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