finish sim
This commit is contained in:
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5eebe6e922
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d345fed4e7
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@ -11,3 +11,4 @@
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*.bin
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*.dat
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*.png
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!im.tif
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@ -1,114 +0,0 @@
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######################################################################
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#
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# DESCRIPTION: Verilator Example: Small Makefile
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#
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# This calls the object directory makefile. That allows the objects to
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# be placed in the "current directory" which simplifies the Makefile.
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#
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# This file ONLY is placed under the Creative Commons Public Domain, for
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# any use, without warranty, 2020 by Wilson Snyder.
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# SPDX-License-Identifier: CC0-1.0
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#
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######################################################################
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# Check for sanity to avoid later confusion
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ifneq ($(words $(CURDIR)),1)
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$(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
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endif
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######################################################################
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# Set up variables
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# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
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# package install, and verilator is in your path. Otherwise find the
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# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
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ifeq ($(VERILATOR_ROOT),)
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VERILATOR = verilator
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VERILATOR_COVERAGE = verilator_coverage
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else
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export VERILATOR_ROOT
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VERILATOR = $(VERILATOR_ROOT)/bin/verilator
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VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
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endif
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VERILATOR_FLAGS =
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# Generate SystemC in executable form
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VERILATOR_FLAGS += -sc --exe
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# Generate makefile dependencies (not shown as complicates the Makefile)
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#VERILATOR_FLAGS += -MMD
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# Optimize
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# VERILATOR_FLAGS += -x-assign fast
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# Warn abount lint issues; may not want this on less solid designs
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VERILATOR_FLAGS += -Wall
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# Make waveforms
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VERILATOR_FLAGS += --trace
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# Check SystemVerilog assertions
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VERILATOR_FLAGS += --assert
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# Generate coverage analysis
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# VERILATOR_FLAGS += --coverage
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# Run Verilator in debug mode
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#VERILATOR_FLAGS += --debug
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# Add this trace to get a backtrace in gdb
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#VERILATOR_FLAGS += --gdbbt
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# Specify top module
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TOP_MODULE = demosaic2
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VERILATOR_FLAGS += -top $(TOP_MODULE)
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# Input files for Verilator
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VERILATOR_INPUT = ../demosaic2.v sc_demosaic.cpp
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# Check if SC exists via a verilator call (empty if not)
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SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
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######################################################################
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ifneq ($(SYSTEMC_EXISTS),)
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default: run
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else
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default: nosc
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endif
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run:
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@echo
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@echo "-- Verilator tracing example"
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@echo
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@echo "-- VERILATE ----------------"
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$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
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@echo
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@echo "-- COMPILE -----------------"
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# To compile, we can either
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# 1. Pass --build to Verilator by editing VERILATOR_FLAGS above.
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# 2. Or, run the make rules Verilator does:
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# $(MAKE) -j -C obj_dir -f Vtop.mk
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# 3. Or, call a submakefile where we can override the rules ourselves:
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$(MAKE) -j -C obj_dir -f V$(TOP_MODULE).mk
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@echo
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@echo "-- RUN ---------------------"
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@rm -rf logs
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@mkdir -p logs
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obj_dir/V$(TOP_MODULE) +trace
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@echo
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@echo "-- DONE --------------------"
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@echo "To see waveforms, open vlt_dump.vcd in a waveform viewer"
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@echo
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######################################################################
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# Other targets
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nosc:
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@echo
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@echo "%Skip: SYSTEMC_INCLUDE not in environment"
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@echo "(If you have SystemC see the README, and rebuild Verilator)"
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@echo
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show-config:
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$(VERILATOR) -V
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maintainer-copy::
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clean mostlyclean distclean maintainer-clean::
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-rm -rf obj_dir logs *.log *.dmp *.vpd coverage.dat core
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@ -1,208 +0,0 @@
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// For std::unique_ptr
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#include <memory>
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// SystemC global header
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#include <systemc>
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// Include common routines
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#include <sys/stat.h> // mkdir
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#include <verilated.h>
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#include <verilated_vcd_sc.h>
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// Include model header, generated from Verilating "demo.v"
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#include "Vdemosaic2.h"
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// Handle file
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#include <fstream>
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#include <iostream>
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#define IM_WIDTH 512
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#define IM_HEIGHT 256
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#define IM_SIZE (IM_WIDTH * IM_HEIGHT)
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using namespace std;
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using namespace sc_core;
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using namespace sc_dt;
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int sc_main(int argc, char* argv[]) {
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// Open image
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ifstream in_image;
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ofstream out_image;
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in_image.open("./transform/test.bin", ios::in | ios::binary);
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out_image.open("./transform/out.bin", ios::out | ios::binary);
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if (!in_image.is_open()) {
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cout << "Open image fail" << endl;
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exit(0);
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} else {
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cout << "Ready to sim" << endl;
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}
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// Read image
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uint8_t buf[IM_SIZE * 2] = {0};
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in_image.read((char*)buf, IM_SIZE * 2);
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// for (uint32_t i = 0; i < IM_SIZE * 2; i++)
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// printf("0x%02x\t", buf[i]);
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in_image.close();
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// Reshape data
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uint16_t image[IM_HEIGHT][IM_WIDTH] = {0};
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uint32_t i = 0;
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for (int y = 0; y < IM_HEIGHT; y++) {
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for (int x = 0; x < IM_WIDTH; x++) {
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image[y][x] = (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
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i++;
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}
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}
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// This is a more complicated example, please also see the simpler
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// examples/make_hello_c.
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// Create logs/ directory in case we have traces to put under it
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Verilated::mkdir("logs");
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// Set debug level, 0 is off, 9 is highest presently used
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// May be overridden by commandArgs argument parsing
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Verilated::debug(0);
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// Randomization reset policy
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// May be overridden by commandArgs argument parsing
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Verilated::randReset(2);
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// Before any evaluation, need to know to calculate those signals only used
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// for tracing
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Verilated::traceEverOn(true);
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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// This needs to be called before you create any model
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Verilated::commandArgs(argc, argv);
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// General logfile
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std::ios::sync_with_stdio();
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// Define clocks
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sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
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// Define interconnect
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sc_signal<bool> reset;
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sc_signal<bool> in_en;
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sc_signal<bool> in_que;
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sc_signal<uint32_t> data_in[3];
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sc_signal<bool> out_en;
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sc_signal<uint32_t> out_r, out_g, out_b;
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// Construct the Verilated model, from inside Vtop.h
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at
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// end
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const std::unique_ptr<Vdemosaic2> demo{new Vdemosaic2{"demo"}};
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// Attach Vtop's signals to this upper model
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demo->clk(clk);
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demo->reset(reset);
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demo->data_en(in_en);
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demo->data_que(in_que);
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demo->data_in[0](data_in[0]);
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demo->data_in[1](data_in[1]);
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demo->data_in[2](data_in[2]);
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demo->out_en(out_en);
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demo->out_r(out_r);
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demo->out_g(out_g);
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demo->out_b(out_b);
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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sc_start(SC_ZERO_TIME);
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// If verilator was invoked with --trace argument,
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// and if at run time passed the +trace argument, turn on tracing
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VerilatedVcdSc* tfp = nullptr;
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const char* flag = Verilated::commandArgsPlusMatch("trace");
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if (flag && 0 == std::strcmp(flag, "+trace")) {
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std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
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tfp = new VerilatedVcdSc;
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demo->trace(tfp, 99); // Trace 99 levels of hierarchy
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Verilated::mkdir("logs");
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tfp->open("logs/vlt_dump.vcd");
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}
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// Simulate until $finish
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bool flag_posedge = 0;
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bool clk_last = 0, clk_now = 0;
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uint16_t pos_x = 0, pos_y = 0;
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uint16_t out[IM_SIZE] = {0};
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uint32_t out_head = 0;
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while (!Verilated::gotFinish()) {
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// Flush the wave files each cycle so we can immediately see the output
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// Don't do this in "real" programs, do it in an abort() handler instead
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if (tfp) tfp->flush();
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// Apply inputs
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if (sc_time_stamp() < sc_time(10, SC_NS)) {
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reset.write(1); // Assert reset
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} else {
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reset.write(0); // Deassert reset
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}
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// Clock posedge generatre
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clk_now = clk.read();
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if (!clk_last && clk_now)
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flag_posedge = 1;
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clk_last = clk_now;
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// Send image data and Read RGB image data
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if (sc_time_stamp() > sc_time(10, SC_NS) && flag_posedge) {
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flag_posedge = 0;
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// Send image data to demosaic
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if (in_que.read() && pos_y < IM_HEIGHT - 2) {
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in_en.write(1);
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printf("x=%3d, y=%3d, data=0x%04x\t", pos_x, pos_y, image[pos_y + 0][pos_x]);
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printf("x=%3d, y=%3d, data=0x%04x\t", pos_x, pos_y, image[pos_y + 1][pos_x]);
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printf("x=%3d, y=%3d, data=0x%04x\n", pos_x, pos_y, image[pos_y + 2][pos_x]);
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data_in[0].write(image[pos_y + 0][pos_x++]);
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data_in[1].write(image[pos_y + 1][pos_x++]);
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data_in[2].write(image[pos_y + 2][pos_x++]);
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if (pos_x >= IM_WIDTH) {
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pos_x = 0;
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pos_y++;
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}
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} else {
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in_en.write(0);
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}
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// Read image data
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if (out_en.read()) {
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out[out_head++] = ((uint8_t)(out_r.read() * 5 / 12) << 10) +
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((uint8_t)(out_g.read() * 5 / 12) << 5) +
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((uint8_t)(out_b.read() * 5 / 12) << 0);
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}
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}
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if (sc_time_stamp() > sc_time(2600, SC_US))
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break;
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// Simulate 1ns
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sc_start(1, SC_NS);
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}
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// Final model cleanup
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demo->final();
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// Close trace if opened
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if (tfp) {
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tfp->close();
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tfp = nullptr;
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}
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// Save final output image
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for (uint32_t i = 0; i < IM_SIZE; i++) {
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buf[i * 2] = (out[i] & 0xffff0000) >> 16;
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buf[i * 2 + 1] = (out[i] & 0x0000ffff);
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}
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out_image.write((const char*)buf, 2 * IM_SIZE);
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out_image.close();
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// Return good completion status
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return 0;
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}
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@ -1,169 +0,0 @@
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`timescale 1ns/10ps
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`define End_CYCLE 100000000
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`define cycle 40.0
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`define PAT "./test.dat"
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`define OUT_F "./test.raw"
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module tb_demosaic();
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parameter WIDTH = 512;
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parameter HEIGHT = 256;
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parameter IMG_SIZE = WIDTH * HEIGHT;
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integer out_f, i, in_count, cycle_count;
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reg clk;
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reg reset;
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reg in_en;
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reg flag;
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wire wr_r, wr_g, wr_b;
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wire done;
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wire [13:0] addr_r, addr_g, addr_b;
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wire [7:0] wdata_r, wdata_g, wdata_b;
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reg [7:0] pixel, rdata_r, rdata_g, rdata_b;
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reg [7:0] PAT [0:IMG_SIZE-1];
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reg [7:0] MEM_R [0:IMG_SIZE-1];
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reg [7:0] MEM_G [0:IMG_SIZE-1];
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reg [7:0] MEM_B [0:IMG_SIZE-1];
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demosaic #(
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WIDTH,
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HEIGHT
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) u_demosaic (
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.clk(clk),
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.reset(reset),
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.in_en(in_en),
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.data_in(pixel),
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.wr_r(wr_r),
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.addr_r(addr_r),
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.wdata_r(wdata_r),
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.rdata_r(rdata_r),
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.wr_g(wr_g),
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.addr_g(addr_g),
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.wdata_g(wdata_g),
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.rdata_g(rdata_g),
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.wr_b(wr_b),
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.addr_b(addr_b),
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.wdata_b(wdata_b),
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.rdata_b(rdata_b),
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.done(done)
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);
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||||
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||||
initial begin
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out_f = $fopen(`OUT_F, "wb");
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end
|
||||
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||||
initial begin
|
||||
$readmemh(`PAT, PAT);
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||||
end
|
||||
|
||||
initial begin
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||||
clk = 0;
|
||||
reset = 0;
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||||
in_en = 0;
|
||||
in_count = 0;
|
||||
cycle_count = 0;
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||||
pixel = 'hx;
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||||
rdata_r = 'hx;
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||||
rdata_g = 'hx;
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||||
rdata_b = 'hx;
|
||||
flag = 0;
|
||||
for(i = 0; i < IMG_SIZE; i = i + 1) begin
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||||
MEM_R[i] = 0;
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||||
MEM_G[i] = 0;
|
||||
MEM_B[i] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
always #(`cycle/2) clk = ~clk;
|
||||
|
||||
initial begin
|
||||
$display("********************************************************************");
|
||||
$display("** Simulation Start **");
|
||||
$display("********************************************************************");
|
||||
@(posedge clk); #2 reset = 1'b1;
|
||||
#(`cycle*2);
|
||||
@(posedge clk); #2 reset = 1'b0;
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||||
end
|
||||
|
||||
initial begin
|
||||
@(posedge clk);
|
||||
# (`cycle*3) flag = 1;
|
||||
end
|
||||
|
||||
always @ (negedge clk or posedge reset) begin // send mosaic image
|
||||
if(reset) begin
|
||||
pixel <= 0;
|
||||
in_en <= 0;
|
||||
end
|
||||
else begin
|
||||
if(flag) begin
|
||||
if(in_count <= IMG_SIZE-1) begin
|
||||
in_en <= 1;
|
||||
in_count <= in_count + 1;
|
||||
pixel <= PAT[in_count];
|
||||
end
|
||||
else begin
|
||||
in_en <= 0;
|
||||
pixel <= 'hx;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @ (negedge clk) begin // read memory, send data to module
|
||||
if(!wr_r)
|
||||
rdata_r <= MEM_R[addr_r];
|
||||
else
|
||||
rdata_r <= 'hx;
|
||||
if(!wr_g)
|
||||
rdata_g <= MEM_G[addr_g];
|
||||
else
|
||||
rdata_g <= 'hx;
|
||||
if(!wr_b)
|
||||
rdata_b <= MEM_B[addr_b];
|
||||
else
|
||||
rdata_b <= 'hx;
|
||||
end
|
||||
|
||||
always @ (negedge clk) begin // write memory, read data and save
|
||||
if(wr_r) begin
|
||||
MEM_R[addr_r] <= wdata_r;
|
||||
end
|
||||
if(wr_g) begin
|
||||
MEM_G[addr_g] <= wdata_g;
|
||||
end
|
||||
if(wr_b) begin
|
||||
MEM_B[addr_b] <= wdata_b;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin // count cycle
|
||||
cycle_count <= cycle_count + 1;
|
||||
if(cycle_count >= `End_CYCLE) begin
|
||||
$display("********************************************************************");
|
||||
$display("** Fail waiting done signal **");
|
||||
$display("** You can increase END_CYCLE by yourself **");
|
||||
$display("********************************************************************");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin // check result
|
||||
if(done) begin
|
||||
for(i = 0; i < IMG_SIZE; i = i + 1) begin
|
||||
$fwrite(out_f, "%c", MEM_R[i]);
|
||||
$fwrite(out_f, "%c", MEM_G[i]);
|
||||
$fwrite(out_f, "%c", MEM_B[i]);
|
||||
end
|
||||
$fclose(out_f);
|
||||
$display("********************************************************************");
|
||||
$display("** Simulation completed successfully! **");
|
||||
$display("********************************************************************");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
6
isp.v
6
isp.v
|
@ -1,8 +1,8 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
module isp #(
|
||||
parameter IN_WIDTH = 1936,
|
||||
parameter IN_HEIGHT = 1088,
|
||||
parameter IN_WIDTH = 700,
|
||||
parameter IN_HEIGHT = 500,
|
||||
parameter OUT_WIDTH = 640,
|
||||
parameter OUT_HEIGHT = 480,
|
||||
parameter COLOR_DEPTH = 8,
|
||||
|
@ -66,6 +66,8 @@ module isp #(
|
|||
);
|
||||
|
||||
crop #(
|
||||
.IN_WIDTH(IN_WIDTH),
|
||||
.IN_HEIGHT(IN_HEIGHT),
|
||||
.OUT_WIDTH(OUT_WIDTH),
|
||||
.OUT_HEIGHT(OUT_HEIGHT),
|
||||
.COLOR_DEPTH(COLOR_DEPTH)
|
||||
|
|
|
@ -44,6 +44,8 @@ VERILATOR_FLAGS += -Wall
|
|||
VERILATOR_FLAGS += --trace
|
||||
# Check SystemVerilog assertions
|
||||
VERILATOR_FLAGS += --assert
|
||||
# Enable multithreading
|
||||
# VERILATOR_FLAGS += --threads 4
|
||||
# Generate coverage analysis
|
||||
# VERILATOR_FLAGS += --coverage
|
||||
# Run Verilator in debug mode
|
||||
|
|
|
@ -17,9 +17,12 @@
|
|||
#include <fstream>
|
||||
#include <iostream>
|
||||
|
||||
#define IM_WIDTH 1936
|
||||
#define IM_HEIGHT 1088
|
||||
#define IM_SIZE (IM_WIDTH * IM_HEIGHT)
|
||||
#define IN_WIDTH 700
|
||||
#define IN_HEIGHT 500
|
||||
#define IN_SIZE (IN_WIDTH * IN_HEIGHT)
|
||||
#define OUT_WIDTH 640
|
||||
#define OUT_HEIGHT 480
|
||||
#define OUT_SIZE (OUT_WIDTH * OUT_HEIGHT)
|
||||
|
||||
using namespace std;
|
||||
using namespace sc_core;
|
||||
|
@ -37,11 +40,9 @@ SC_MODULE (TB_ISP) {
|
|||
sc_in<bool> im_en;
|
||||
sc_in<uint32_t> im_data;
|
||||
|
||||
// uint16_t image[IM_HEIGHT][IM_WIDTH];
|
||||
// uint32_t out[IM_HEIGHT][IM_WIDTH];
|
||||
// uint32_t out_head = 0;
|
||||
unique_ptr<uint16_t[]> image = make_unique<uint16_t[]>(IM_SIZE);
|
||||
unique_ptr<uint32_t[]> out = make_unique<uint32_t[]>(IM_SIZE);
|
||||
sc_out<bool> is_done;
|
||||
unique_ptr<uint16_t[]> image;
|
||||
unique_ptr<uint32_t[]> out = make_unique<uint32_t[]>(OUT_SIZE);
|
||||
|
||||
SC_CTOR (TB_ISP) {
|
||||
SC_CTHREAD(send_Data, clk.pos());
|
||||
|
@ -54,21 +55,21 @@ SC_MODULE (TB_ISP) {
|
|||
uint16_t pos_x = 0, pos_y = 0;
|
||||
while (true)
|
||||
{
|
||||
if (data_que.read() && pos_y < IM_HEIGHT - 2) {
|
||||
if (data_que.read() && pos_y < IN_HEIGHT - 2) {
|
||||
data_en.write(1);
|
||||
|
||||
printf("x=%3d, y=%3d, data=0x%04x\t", pos_x, pos_y, image[( pos_y + 0 ) * IM_WIDTH + pos_x]);
|
||||
printf("x=%3d, y=%3d, data=0x%04x\t", pos_x, pos_y, image[( pos_y + 1 ) * IM_WIDTH + pos_x]);
|
||||
printf("x=%3d, y=%3d, data=0x%04x\n", pos_x, pos_y, image[( pos_y + 2 ) * IM_WIDTH + pos_x]);
|
||||
printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y, image[( pos_y + 0 ) * IN_WIDTH + pos_x]);
|
||||
printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y, image[( pos_y + 1 ) * IN_WIDTH + pos_x]);
|
||||
printf("x=%4d, y=%4d, data=0x%04x\n", pos_x, pos_y, image[( pos_y + 2 ) * IN_WIDTH + pos_x]);
|
||||
|
||||
data_out[0].write(image[( pos_y + 0 ) * IM_WIDTH + pos_x]);
|
||||
data_out[1].write(image[( pos_y + 1 ) * IM_WIDTH + pos_x]);
|
||||
data_out[2].write(image[( pos_y + 2 ) * IM_WIDTH + pos_x]);
|
||||
data_out[0].write(image[( pos_y + 0 ) * IN_WIDTH + pos_x]);
|
||||
data_out[1].write(image[( pos_y + 1 ) * IN_WIDTH + pos_x]);
|
||||
data_out[2].write(image[( pos_y + 2 ) * IN_WIDTH + pos_x]);
|
||||
|
||||
wait(1);
|
||||
data_en.write(0);
|
||||
|
||||
if (pos_x++ >= IM_WIDTH) {
|
||||
if (pos_x++ >= IN_WIDTH) {
|
||||
pos_x = 0;
|
||||
pos_y++;
|
||||
}
|
||||
|
@ -82,18 +83,31 @@ SC_MODULE (TB_ISP) {
|
|||
}
|
||||
|
||||
void read_Data(void) {
|
||||
is_done.write(0);
|
||||
uint16_t pos_x = 0, pos_y = 0;
|
||||
uint32_t last_data = 0;
|
||||
uint16_t cnt = 0;
|
||||
while (true)
|
||||
{
|
||||
if (im_en.read()) {
|
||||
out[pos_y * IM_WIDTH + pos_x] = im_data.read();
|
||||
out[pos_y * OUT_WIDTH + pos_x] = im_data.read();
|
||||
|
||||
if (pos_x++ >= IM_WIDTH) {
|
||||
if (pos_x++ >= OUT_WIDTH) {
|
||||
pos_x = 0;
|
||||
pos_y++;
|
||||
}
|
||||
}
|
||||
|
||||
if (last_data == im_data.read()) {
|
||||
cnt++;
|
||||
if (cnt >= 100) {
|
||||
is_done.write(1);
|
||||
}
|
||||
} else {
|
||||
cnt = 0;
|
||||
}
|
||||
last_data = im_data.read();
|
||||
|
||||
wait();
|
||||
}
|
||||
}
|
||||
|
@ -104,7 +118,7 @@ int sc_main(int argc, char* argv[]) {
|
|||
// Open image
|
||||
ifstream in_image;
|
||||
ofstream out_image;
|
||||
in_image.open("../Demosaic/sim/transform/test.bin", ios::in | ios::binary);
|
||||
in_image.open("./transform/test.bin", ios::in | ios::binary);
|
||||
out_image.open("./out.bin", ios::out | ios::binary);
|
||||
if (!in_image.is_open()) {
|
||||
cout << "Open image fail" << endl;
|
||||
|
@ -114,18 +128,18 @@ int sc_main(int argc, char* argv[]) {
|
|||
}
|
||||
|
||||
// Read image
|
||||
// uint8_t buf[IM_SIZE * 2] = {0};
|
||||
auto buf = make_unique<uint8_t[]>(2 * IM_SIZE);
|
||||
// vector<vector<uint8_t>> buf(IM_HEIGHT, vector<uint8_t>(IM_WIDTH, 0));
|
||||
in_image.read((char*)buf.get(), IM_SIZE * 2);
|
||||
// uint8_t buf[IN_SIZE * 2] = {0};
|
||||
auto buf = make_unique<uint8_t[]>(2 * IN_SIZE);
|
||||
// vector<vector<uint8_t>> buf(IN_HEIGHT, vector<uint8_t>(IN_WIDTH, 0));
|
||||
in_image.read((char*)buf.get(), IN_SIZE * 2);
|
||||
in_image.close();
|
||||
// Reshape data
|
||||
// uint16_t image[IM_HEIGHT][IM_WIDTH] = {0};
|
||||
auto image = make_unique<uint16_t[]>(IM_SIZE);
|
||||
// uint16_t image[IN_HEIGHT][IN_WIDTH] = {0};
|
||||
auto image = make_unique<uint16_t[]>(IN_SIZE);
|
||||
uint32_t i = 0;
|
||||
for (int y = 0; y < IM_HEIGHT; y++) {
|
||||
for (int x = 0; x < IM_WIDTH; x++) {
|
||||
image[y * IM_WIDTH + x] = (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
|
||||
for (int y = 0; y < IN_HEIGHT; y++) {
|
||||
for (int x = 0; x < IN_WIDTH; x++) {
|
||||
image[y * IN_WIDTH + x] = (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
|
||||
i += 2;
|
||||
}
|
||||
}
|
||||
|
@ -167,6 +181,8 @@ int sc_main(int argc, char* argv[]) {
|
|||
sc_signal<bool> out_en;
|
||||
sc_signal<uint32_t> data_out;
|
||||
|
||||
sc_signal<bool> flag_done;
|
||||
|
||||
|
||||
// Construct the Verilated model, from inside Visp.h
|
||||
// Using unique_ptr is similar to "Visp* isp = new Visp" then deleting at end
|
||||
|
@ -195,6 +211,7 @@ int sc_main(int argc, char* argv[]) {
|
|||
tb_isp.im_clk(out_clk);
|
||||
tb_isp.im_en(out_en);
|
||||
tb_isp.im_data(data_out);
|
||||
tb_isp.is_done(flag_done);
|
||||
tb_isp.image = move(image);
|
||||
|
||||
// You must do one evaluation before enabling waves, in order to allow
|
||||
|
@ -226,6 +243,9 @@ int sc_main(int argc, char* argv[]) {
|
|||
reset.write(0); // Deassert reset
|
||||
}
|
||||
|
||||
if (flag_done.read())
|
||||
break;
|
||||
|
||||
// Simulate 1ns
|
||||
sc_start(1, SC_NS);
|
||||
}
|
||||
|
@ -240,9 +260,10 @@ int sc_main(int argc, char* argv[]) {
|
|||
}
|
||||
|
||||
// Save output image
|
||||
for (int y = 0; y < IM_HEIGHT; y++)
|
||||
for(int x = 0; x < IM_WIDTH; x++)
|
||||
out_image.write((const char *)&tb_isp.out[y * IM_WIDTH + x], sizeof(tb_isp.out[0]));
|
||||
cout << "Ready to save raw RGB image" << endl;
|
||||
for (int y = 0; y < OUT_HEIGHT; y++)
|
||||
for(int x = 0; x < OUT_WIDTH; x++)
|
||||
out_image.write((const char *)&tb_isp.out[y * OUT_WIDTH + x], sizeof(tb_isp.out[0]));
|
||||
out_image.close();
|
||||
|
||||
// Return good completion status
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
import imageio
|
||||
import numpy as np
|
||||
|
||||
cut_width = 1936
|
||||
cut_height = 1088
|
||||
cut_width = 700
|
||||
cut_height = 500
|
||||
|
||||
if __name__ == '__main__':
|
||||
# txt = open('./test.dat', 'w')
|
Loading…
Reference in New Issue