SikongJueluo/ISP
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix demosaic not work correctly and polish project manage

Browse Source
This commit is contained in:
SikongJueluo
2024-10-25 23:12:57 +08:00
parent 1ab1467569
commit a8fa609228
17 changed files with 493 additions and 140 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
rtl/BayerProcess/DPC.sv
View File

@@ -1,10 +1,11 @@
`timescale 1ns / 1ps
module DPC #(
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用
parameter reg [ 4:0] LABLE_ENABLE = 1 // 是否启动坏点标注，DEBUG用
) (
input wire clk,
input wire reset,
@@ -220,18 +221,20 @@ module DPC #(
channel_cache_correct_final <= channel_cache_correct2[flag_which_dict];
case (flag_which_dict)
2'b00:
flag_if_need_corection <= grad_h_cache2[1] > 4 * (grad_h_cache2[0] + grad_h_cache2[2]);
flag_if_need_corection <= grad_h_cache2[1] / 4 > (grad_h_cache2[0] + grad_h_cache2[2]);
2'b01:
flag_if_need_corection <= grad_v_cache2[1] > 4 * (grad_v_cache2[0] + grad_v_cache2[2]);
flag_if_need_corection <= grad_v_cache2[1] / 4 > (grad_v_cache2[0] + grad_v_cache2[2]);
2'b10:
flag_if_need_corection <= grad_45_cache2[1] > 3 * (grad_45_cache2[0] + grad_45_cache2[2]);
flag_if_need_corection <= grad_45_cache2[1] / 4 > (grad_45_cache2[0] + grad_45_cache2[2]);
2'b11:
flag_if_need_corection <= grad_135_cache2[1] > 3*(grad_135_cache2[0] + grad_135_cache2[2]);
flag_if_need_corection <= grad_135_cache2[1]/4 > (grad_135_cache2[0] + grad_135_cache2[2]);
endcase
end
if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值
out_data <= (flag_if_need_corection) ? (channel_cache_correct_final) : (channel_cache4);
if (MODULE_ENABLE)
out_data <= (flag_if_need_corection)?((LABLE_ENABLE)?(12'hFFF):(channel_cache_correct_final)):(channel_cache4);
else out_data <= channel_cache4;
end
end
end
@@ -296,3 +299,4 @@ module DPC #(
endmodule

4
rtl/BayerProcess/Demosaic_Pipeline.sv
View File

@@ -58,7 +58,6 @@ module Demosaic_Pipeline #(
raw_type <= RAW_TYPE;
end else if (pipeline_running) begin
// First level pipeline for reading data
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin
@@ -107,7 +106,7 @@ module Demosaic_Pipeline #(
end
if (pipeline_valid[2]) begin
{out_data[2], out_data[1], out_data[0]} <= {red, blue, green};
{out_data[2], out_data[1], out_data[0]} <= {red, green, blue};
out_hsync <= (temp_pos_x2 == 0);
out_fsync <= ((temp_pos_x2 == 0) && (temp_pos_y2 == 0));
end
@@ -119,3 +118,4 @@ module Demosaic_Pipeline #(
// grg rgr bgb gbg 258
endmodule

10
rtl/BayerProcess/Windows.sv
View File

@@ -38,17 +38,21 @@ SHIFT_REG0 -> 1 4 7 . .
. . .
*/
reg firstframedone;
reg [15:0] pos_x, pos_y;
always @(posedge clk) begin
if (reset) begin
pos_x <= 0;
pos_y <= 0;
firstframedone <= 0;
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
pos_x <= (pos_x >= IMAGE_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y <= (pos_x >= IMAGE_WIDTH - 1)?((pos_y >= IMAGE_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
firstframedone <= (pos_x >= IMAGE_WIDTH - 1 && pos_y >= IMAGE_HEIGHT - 1)?(1):(firstframedone);
end else begin
pos_x <= pos_x;
pos_y <= pos_y;
firstframedone <= firstframedone;
end
end
@@ -62,11 +66,13 @@ SHIFT_REG0 -> 1 4 7 . .
for (j = 0; j < WINDOWS_WIDTH; j = j + 1) begin
if (i == WINDOWS_WIDTH - 1) begin
if (j == 0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*i-1];
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1];
end else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
end
end
out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
if (firstframedone) out_valid <= 1;
else
out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
end else begin
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH - 1; i = i + 1) out_data[i] <= out_data[i];
out_valid <= 0;

4
rtl/Color/ColorBlender_Pipeline.sv
View File

@@ -71,9 +71,9 @@ module ColorBlender_Pipeline #(
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_blue}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_red}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;

90
rtl/Color/GammaCorrection_Pipeline.sv
View File

@@ -1,84 +1,42 @@
`timescale 1ns / 1ps
module GammaCorrection_Pipeline #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
module GammaCorrection_Pipeline
import common::*;
#(
parameter bit [4:0] COLOR_DEPTH = 8
) (
input var clk,
input var reset,
input wire in_valid,
output reg out_valid,
input var in_ready,
input var in_valid,
input var [COLOR_DEPTH - 1 : 0] in_data[3],
input wire in_ready,
output wire out_ready,
output var out_ready,
output var out_valid,
output var [COLOR_DEPTH - 1 : 0] out_data[3],
input wire in_hsync,
output wire out_hsync,
output var out_hsync,
output var out_fsync,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
input var [7:0] in_Gtable[256],
input var in_enable
);
Color color;
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
assign out_ready = in_ready;
input wire [7:0] gamma_table[256],
input wire enable
);
reg [7:0] data_cache[3];
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk)
begin
if (reset)
begin
out_en <= 0;
always_ff @(posedge clock) begin : blockName
if (reset) begin
out_valid <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
end else begin
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
end
else
begin
case (state)
READ_DATA:
begin
if (in_en)
begin
data_cache[0] <= in_data[0];
data_cache[1] <= in_data[1];
data_cache[2] <= in_data[2];
end
end
SEND_DATA:
begin
if (in_ready && !in_receive)
begin
out_en <= 1;
if (enable)
begin
out_data[0] <= gamma_table[data_cache[0]];
out_data[1] <= gamma_table[data_cache[1]];
out_data[2] <= gamma_table[data_cache[2]];
end
else
begin
out_data[0] <= data_cache[0];
out_data[1] <= data_cache[1];
out_data[2] <= data_cache[2];
end
end
else
out_en <= 0;
end
default:
;
endcase
end
end

16
rtl/common.sv Normal file
View File

@@ -0,0 +1,16 @@
`default_nettype none
package common;
class Color;
bit [7:0] red;
bit [7:0] green;
bit [7:0] blue;
function new(bit [7:0] red, bit [7:0] green, bit [7:0] blue);
this.red = red;
this.green = green;
this.blue = blue;
endfunction //new()
endclass //Color
endpackage

12
rtl/isp_Pipeline.sv
View File

@@ -76,10 +76,12 @@ module isp_Pipeline #(
);
DPC #(
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT(IN_HEIGHT),
.RAW_TYPE (3),
.DATA_WIDTH (DATA_WIDTH)
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (3),
.DATA_WIDTH (DATA_WIDTH),
.MODULE_ENABLE(1),
.LABLE_ENABLE (1)
) DPC_inst (
.clk (clk),
.reset (reset),
@@ -113,7 +115,7 @@ module isp_Pipeline #(
.WINDOW_LENGTH(3),
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (3),
.RAW_TYPE (0),
.DATA_WIDTH (DATA_WIDTH)
) Demosaic_inst (
.clk (clk),