126 lines
4.3 KiB
Systemverilog
126 lines
4.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module Windows #(
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parameter DATA_WIDTH = 16,
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parameter IMAGE_WIDTH = 1936,
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parameter IMAGE_HEIGHT = 1088,
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parameter WINDOWS_WIDTH = 3,
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parameter WINDOWS_ANCHOR_X = 1, //禁止大于WINDOWS_WIDTH-1
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parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1
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) (
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// 基本信号
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input wire clk,
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input wire reset,
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// 数据线
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input wire [DATA_WIDTH - 1:0] in_data,
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output reg [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线
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// 有效信号
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input wire in_valid, // 上一模块输出数据有效
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output reg out_valid, // 当前模块输出数据有效
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// 准备信号 Windows模块无法停止，因此默认不处理准备信号
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input wire in_ready,
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output wire out_ready
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);
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assign out_ready = 1'b1;
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reg [DATA_WIDTH - 1:0] regx_in_data [WINDOWS_WIDTH-1];
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reg [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
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reg [WINDOWS_WIDTH - 2:0] regx_in_valid, regx_out_valid;
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reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
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/* outdata[x]:
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SHIFT_REG1 -> 0 3 6 . .
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SHIFT_REG0 -> 1 4 7 . .
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in_data -> 2 5 8 . .
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. . .
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. . .
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*/
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reg firstframedone;
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reg [15:0] pos_x, pos_y;
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always @(posedge clk) begin
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if (reset) begin
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pos_x <= 0;
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pos_y <= 0;
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firstframedone <= 0;
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end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
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pos_x <= (pos_x >= IMAGE_WIDTH - 1) ? (0) : (pos_x + 1);
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pos_y <= (pos_x >= IMAGE_WIDTH - 1)?((pos_y >= IMAGE_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
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firstframedone <= (pos_x >= IMAGE_WIDTH - 1 && pos_y >= IMAGE_HEIGHT - 1)?(1):(firstframedone);
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end else begin
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pos_x <= pos_x;
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pos_y <= pos_y;
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firstframedone <= firstframedone;
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end
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end
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integer i, j;
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always @(posedge clk) begin
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if (reset) begin
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for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH; i = i + 1) out_data[i] <= 0;
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out_valid <= 0;
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end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
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for (i = 0; i < WINDOWS_WIDTH; i = i + 1) begin
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for (j = 0; j < WINDOWS_WIDTH; j = j + 1) begin
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if (i == WINDOWS_WIDTH - 1) begin
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if (j == 0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
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else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1];
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end else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
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end
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end
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if (firstframedone) out_valid <= 1;
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else
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out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
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end else begin
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for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH - 1; i = i + 1) out_data[i] <= out_data[i];
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out_valid <= 0;
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end
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end
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always @(posedge clk) begin
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if (reset)
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for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1)
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for (j = 0; j < WINDOWS_WIDTH - 1; j = j + 1) data_out_shift[i][j] <= 0;
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else
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for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
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for (j = 0; j < 2 * (WINDOWS_WIDTH - 1); j = j + 1) begin
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if (i == WINDOWS_WIDTH - 2 && j == 0) data_out_shift[i][j] <= in_data;
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else if (j == 0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
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else data_out_shift[i][j] <= data_out_shift[i][j-1];
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end
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end
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end
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always @(*) begin
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for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
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if (i == 0) regx_in_data[i] = in_data;
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else regx_in_data[i] = regx_out_data[i-1];
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end
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for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
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if (i == 0) regx_in_valid[i] = in_valid;
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else regx_in_valid[i] = regx_out_valid[i-1];
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end
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end
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generate
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genvar o;
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for (o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin : shift_register
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SHIFT_REGISTER #(
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.DATA_WIDTH (DATA_WIDTH),
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.IMAGE_WIDTH(IMAGE_WIDTH),
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.IFOUTIMME (1'b1)
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) shift_registerx (
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.clk (clk),
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.reset (reset),
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.in_data (regx_in_data[o]),
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.out_data (regx_out_data[o]),
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.in_valid (regx_in_valid[o]),
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.out_valid(regx_out_valid[o])
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);
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end
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endgenerate
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endmodule
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