switch lsp to clangd and reconstruct project
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95
rtl/RAM/DiffWidthSyncFIFO.sv
Executable file
95
rtl/RAM/DiffWidthSyncFIFO.sv
Executable file
@@ -0,0 +1,95 @@
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`timescale 1ns / 1ps
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module DiffWidthSyncFIFO #(
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parameter reg [7:0] DATA_WIDTH = 8,
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parameter reg [7:0] DATA_DEPTH = 12,
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parameter reg [7:0] READ_DEPTH = 3,
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parameter reg [7:0] WRITE_DEPTH = 4
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) (
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input wire clk,
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input wire reset,
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input wire read_ready,
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output reg read_en,
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output reg [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH],
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output wire write_ready,
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input wire write_en,
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input wire [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH]
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);
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reg [DATA_WIDTH - 1 : 0] data[DATA_DEPTH];
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reg [7:0] occupancy;
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reg [7:0] cnt_read, cnt_write;
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reg [7:0] wi, ri;
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reg read_finish, write_finish;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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occupancy <= 0;
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end
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else begin
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if (read_finish && write_finish) begin
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occupancy <= occupancy + (WRITE_DEPTH - READ_DEPTH);
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end
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else if (read_finish) begin
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occupancy <= occupancy - READ_DEPTH;
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end
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else if (write_finish) begin
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occupancy <= occupancy + WRITE_DEPTH;
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end
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else begin
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occupancy <= occupancy;
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end
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end
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end
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// write data to fifo
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assign write_ready = ((DATA_DEPTH - occupancy) >= WRITE_DEPTH && !write_en) ? 1 : 0;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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cnt_write <= 0;
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wi <= 0;
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write_finish <= 0;
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end else begin
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if (write_en && (DATA_DEPTH - occupancy) >= WRITE_DEPTH) begin
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for (wi = 0; wi < WRITE_DEPTH; wi = wi + 1) begin
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data[cnt_write] <= write_data[wi];
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if (cnt_write < DATA_DEPTH - 1) cnt_write <= cnt_write + 1;
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else cnt_write <= 0;
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end
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write_finish <= 1;
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end else begin
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write_finish <= 0;
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end
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end
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end
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integer i;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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for (i = 0; i < READ_DEPTH; i = i + 1) begin
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read_data[i] <= 0;
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end
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ri <= 0;
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read_en <= 0;
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cnt_read <= 0;
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read_finish <= 0;
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end else begin
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if (read_ready && occupancy >= READ_DEPTH) begin
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read_en <= 1;
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for (ri = 0; ri < READ_DEPTH; ri = ri + 1) begin
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read_data[ri] <= data[cnt_read];
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if (cnt_read < DATA_DEPTH - 1) cnt_read <= cnt_read + 1;
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else cnt_read <= 0;
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end
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read_finish <= 1;
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end else begin
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read_en <= 0;
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read_finish <= 0;
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end
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end
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end
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endmodule
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92
rtl/RAM/RGB_to_RAM.v
Executable file
92
rtl/RAM/RGB_to_RAM.v
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@@ -0,0 +1,92 @@
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`timescale 1ns/1ps
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module RGB_to_RAM #(
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parameter COLOR_DEPTH = 8,
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parameter FIFO_SIZE = 128
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) (
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input clk,
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input reset,
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// 数据输入
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output reg in_que,
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input in_en,
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input [3 * COLOR_DEPTH - 1:0] data_in,
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// 写入SRAM
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input write_que,
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output write_en,
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output [15:0] data_write
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);
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// 状态机
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localparam READ_DATA = 0;
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localparam SEND_R = 1;
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localparam SEND_GB = 2;
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reg [2:0] state, nextState;
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reg [3 * COLOR_DEPTH - 1:0] data_cache;
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reg [15:0] fifo_data;
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wire fifo_full, fifo_empty;
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async_fifo #(
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.DSIZE(16),
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.ASIZE(FIFO_SIZE)
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) fifo_image (
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.wclk(clk),
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.wrst_n(reset),
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.rclk(clk),
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.rrst_n(reset),
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.winc(in_en),
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.wdata(fifo_data),
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.wfull(fifo_full),
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/* verilator lint_off PINCONNECTEMPTY */
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.awfull(),
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.rinc(write_en),
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.rdata(data_write),
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.rempty(fifo_empty),
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/* verilator lint_off PINCONNECTEMPTY */
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.arempty()
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);
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// 当有数据请求且FIFO不为空时，输出数据
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assign write_en = (write_que && !fifo_empty) ? 1 : 0;
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always @(posedge clk or posedge reset) begin
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if (reset)
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state <= READ_DATA;
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else
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state <= nextState;
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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fifo_data <= 0;
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data_cache <= 0;
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end
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else begin
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case (state)
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// 读取数据
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READ_DATA: begin
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in_que <= 1;
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if (in_en) begin
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data_cache <= data_in;
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nextState <= SEND_R;
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end
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end
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SEND_R: begin
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in_que <= 0;
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fifo_data <= {8'b0, data_cache[3 * COLOR_DEPTH - 1:16]};
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nextState <= SEND_GB;
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end
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SEND_GB: begin
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fifo_data <= data_cache[15:0];
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nextState <= READ_DATA;
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end
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endcase
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end
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end
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endmodule
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29
rtl/RAM/SDRAM.v
Executable file
29
rtl/RAM/SDRAM.v
Executable file
@@ -0,0 +1,29 @@
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module SDRAM (
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input wire clk,
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input wire read_en,
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input wire [31:0] read_addr,
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output wire [31:0] read_data,
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output wire read_ready,
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input wire write_en,
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input wire [31:0] write_addr,
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input reg [31:0] write_data,
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output wire write_ready
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);
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reg [31:0] ram[1920*1080];
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assign read_ready = (!read_en) ? 1 : 0;
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assign write_ready = (!write_en) ? 1 : 0;
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always @(posedge clk) begin
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if (read_en)
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ram[read_addr] <= read_data;
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end
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always @(posedge clk) begin
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if (write_en)
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write_data <= ram[write_addr];
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end
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endmodule
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74
rtl/RAM/tb_DiffWidthSyncFIFO.sv
Executable file
74
rtl/RAM/tb_DiffWidthSyncFIFO.sv
Executable file
@@ -0,0 +1,74 @@
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`timescale 1ns / 1ps
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`include "DiffWidthSyncFIFO.v"
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`default_nettype none
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module tb_DiffWidthSyncFIFO;
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localparam reg [7:0] DATA_WIDTH = 8;
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localparam reg [7:0] DATA_DEPTH = 12;
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localparam reg [7:0] READ_DEPTH = 3;
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localparam reg [7:0] WRITE_DEPTH = 4;
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reg clk;
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reg reset;
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reg write_en;
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reg [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH];
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wire read_en, write_ready, read_ready;
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wire [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH];
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DiffWidthSyncFIFO #(
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.DATA_WIDTH (DATA_WIDTH),
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.DATA_DEPTH (DATA_DEPTH),
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.READ_DEPTH (READ_DEPTH),
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.WRITE_DEPTH(WRITE_DEPTH)
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) inst_fifo (
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.clk (clk),
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.reset(reset),
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.read_ready(read_ready),
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.read_en(read_en),
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.read_data(read_data),
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.write_ready(write_ready),
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.write_en(write_en),
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.write_data(write_data)
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);
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localparam CLK_PERIOD = 10;
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always #(CLK_PERIOD / 2) clk = ~clk;
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initial begin
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$dumpfile("tb_DiffWidthSyncFIFO.vcd");
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$dumpvars(0, tb_DiffWidthSyncFIFO);
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end
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assign read_ready = read_en ? 0 : 1;
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integer j;
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initial begin
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clk = 0;
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reset = 1;
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write_en = 0;
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for(j = 0; j < WRITE_DEPTH; j = j + 1)begin
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write_data[j] = 0;
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end
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end
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integer i;
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initial begin
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#(10 * CLK_PERIOD) reset = 0;
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for (i = 0; i < 20; i = i + 1) begin
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#CLK_PERIOD
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for (j = 0; j < WRITE_DEPTH; j = j + 1) begin
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write_data[j] = {$mti_random} % (32'b1 << DATA_DEPTH);
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end
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write_en = 1;
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#CLK_PERIOD write_en = 0;
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end
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$finish(100 * CLK_PERIOD);
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end
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endmodule
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`default_nettype wire
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