switch lsp to clangd and reconstruct project
This commit is contained in:
99
rtl/Color/ColorBlender.sv
Normal file
99
rtl/Color/ColorBlender.sv
Normal file
@@ -0,0 +1,99 @@
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`timescale 1ns / 1ps
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// 三通道图像合成一个RGB图像
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module ColorBlender #(
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parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
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parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
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) (
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input wire clk,
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input wire reset,
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input wire [16 - 1:0] in_data [3],
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output reg [OUT_DEPTH - 1:0] out_data [3],
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready,
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input wire in_hsync,
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input wire in_fsync,
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output wire out_hsync,
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output wire out_fsync,
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// 颜色校正
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input wire [15:0] gain_red,
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input wire [15:0] gain_green,
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input wire [15:0] gain_blue,
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input wire enable
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);
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localparam PIPELINE = 4;
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reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
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wire pipeline_flag;
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assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_flag;
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//out_valid ：只要本模块有数据要发送就一直拉高
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assign out_valid = pipeline_valid[PIPELINE-1];
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assign out_hsync = pipeline_hsync[PIPELINE-1];
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assign out_fsync = pipeline_fsync[PIPELINE-1];
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reg [32 - 1:0] data_cal0[3];
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reg [32 - 1:0] data_cal1[3];
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reg [32 - 1:0] data_cal2[3];
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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pipeline_valid <= 0;
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pipeline_hsync <= 0;
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pipeline_fsync <= 0;
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for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
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for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
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for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
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for(i=0;i<3;i=i+1) out_data[i] <= 0;
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end else if(pipeline_flag) begin
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/************* 流水 ************/
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pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
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pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
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pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
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/************* 1:计算1 ************/
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if(in_valid) begin
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data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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end
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/************* 2:计算2 ************/
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if(pipeline_valid[0]) begin
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if(enable) begin
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data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
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data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
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data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
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end else begin
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data_cal1[0] <= data_cal0[0] >> 8;
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data_cal1[1] <= data_cal0[1] >> 8;
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data_cal1[2] <= data_cal0[2] >> 8;
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end
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end
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/************* 3:计算3 ************/
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if(pipeline_valid[1]) begin
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data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
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data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
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data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
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end
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/************* 4:发送结果 ************/
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if(pipeline_valid[2]) begin
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out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
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out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
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out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
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end
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end
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end
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endmodule
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106
rtl/Color/GammaCorrection.sv
Executable file
106
rtl/Color/GammaCorrection.sv
Executable file
@@ -0,0 +1,106 @@
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`timescale 1ns / 1ps
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module GammaCorrection #(
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parameter reg [4:0] COLOR_DEPTH = 8
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) (
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input wire clk,
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input wire reset,
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input wire in_en,
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input wire [COLOR_DEPTH - 1 : 0] in_data[3],
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output wire out_ready,
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output wire out_receive,
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output reg out_en,
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output reg [COLOR_DEPTH - 1 : 0] out_data[3],
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input wire in_ready,
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input wire in_receive,
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input wire [7:0] gamma_table[256],
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input wire enable
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);
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reg [2:0] state, nextState;
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localparam reg [2:0] READ_DATA = 0;
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localparam reg [2:0] SEND_DATA = 2;
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reg [7:0] data_cache[3];
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always @(posedge clk)
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begin
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if (reset)
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state <= READ_DATA;
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else
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state <= nextState;
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end
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always @(*)
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begin
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case (state)
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READ_DATA:
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nextState = in_en ? SEND_DATA : READ_DATA;
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SEND_DATA:
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nextState = in_receive ? READ_DATA : SEND_DATA;
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default:
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nextState = READ_DATA;
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endcase
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end
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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always @(posedge clk)
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begin
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if (reset)
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begin
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out_en <= 0;
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out_data[0] <= 0;
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out_data[1] <= 0;
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out_data[2] <= 0;
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data_cache[0] <= 0;
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data_cache[1] <= 0;
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data_cache[2] <= 0;
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end
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else
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begin
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case (state)
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READ_DATA:
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begin
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if (in_en)
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begin
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data_cache[0] <= in_data[0];
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data_cache[1] <= in_data[1];
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data_cache[2] <= in_data[2];
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end
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end
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SEND_DATA:
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begin
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if (in_ready && !in_receive)
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begin
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out_en <= 1;
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if (enable)
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begin
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out_data[0] <= gamma_table[data_cache[0]];
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out_data[1] <= gamma_table[data_cache[1]];
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out_data[2] <= gamma_table[data_cache[2]];
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end
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else
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begin
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out_data[0] <= data_cache[0];
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out_data[1] <= data_cache[1];
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out_data[2] <= data_cache[2];
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end
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end
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else
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out_en <= 0;
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end
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default:
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;
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endcase
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end
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end
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endmodule
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160
rtl/Color/GreyWorld.sv
Executable file
160
rtl/Color/GreyWorld.sv
Executable file
@@ -0,0 +1,160 @@
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`timescale 1ns / 1ps
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// 三通道图像合成一个RGB图像
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module GreyWorld #(
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parameter reg [4:0] COLOR_DEPTH = 8,
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parameter reg [31:0] IM_SIZE = 1920 * 1080
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) (
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input wire clk,
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input wire reset,
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input wire in_en,
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input wire [7:0] in_data[3], // 0:R 1:G 2:B
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output wire out_ready,
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output wire out_receive,
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// 输出相关
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input wire in_ready,
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input wire in_receive,
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output reg out_en,
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output reg [COLOR_DEPTH - 1:0] out_data[3],
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// Gain: red = 0.803881, green = 0.885894, blue = 1.594308
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input wire enable,
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input wire [8:0] flame_rate,
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input wire [15:0] white_gain[3]
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);
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reg [2:0] state, nextState, calState;
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localparam reg [2:0] READ_DATA = 0;
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localparam reg [2:0] CALC_DATA = 1;
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localparam reg [2:0] SEND_DATA = 2;
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reg [8:0] cnt_flame;
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reg [31:0] red_total, green_total, blue_total;
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reg [39:0] r_white_gain[3];
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reg [31:0] data_cal[3], data_cache[3];
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reg [31:0] cnt_pexels;
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reg [39:0] average;
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reg isCal;
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always @(posedge clk) begin
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if (reset) state <= READ_DATA;
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else state <= nextState;
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end
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always @(*) begin
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case (state)
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READ_DATA: nextState = in_en ? CALC_DATA : READ_DATA;
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CALC_DATA: nextState = isCal ? CALC_DATA : SEND_DATA;
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SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
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default: nextState = READ_DATA;
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endcase
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end
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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// assign average = (({8'b0, red_total } + {8'b0, green_total } + {8'b0, blue_total }) << 8) / 3 ;
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// assign isCal = cnt_pexels >= IM_SIZE && cnt_flame == flame_rate;
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always @(posedge clk) begin
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if (reset) begin
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red_total <= 0;
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green_total <= 0;
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blue_total <= 0;
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cnt_flame <= flame_rate;
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cnt_pexels <= 0;
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calState <= 4;
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r_white_gain[0] <= {24'b0, white_gain[0] };
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r_white_gain[1] <= {24'b0, white_gain[1] };
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r_white_gain[2] <= {24'b0, white_gain[2] };
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data_cache[0] <= 0;
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data_cache[1] <= 0;
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data_cache[2] <= 0;
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out_en <= 0;
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out_data[0] <= 0;
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out_data[1] <= 0;
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out_data[2] <= 0;
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end else begin
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case (state)
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READ_DATA: begin
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if (in_en) begin
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data_cache[0] <= {24'b0, in_data[0]};
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data_cache[1] <= {24'b0, in_data[1]};
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data_cache[2] <= {24'b0, in_data[2]};
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if (cnt_flame == flame_rate) begin
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red_total <= red_total + {24'b0, in_data[0]};
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green_total <= green_total + {24'b0, in_data[1]};
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blue_total <= blue_total + {24'b0, in_data[2]};
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end
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if (cnt_pexels <= IM_SIZE) begin
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cnt_pexels <= cnt_pexels + 1;
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end else begin
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cnt_pexels <= 0;
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if (cnt_flame < flame_rate) cnt_flame <= cnt_flame + 1;
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else cnt_flame <= 0;
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if (cnt_pexels >= IM_SIZE && cnt_flame == flame_rate) isCal <= 1;
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end
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end
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end
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CALC_DATA: begin
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if (calState == 0) begin
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average <= {8'b0, red_total } + {8'b0, green_total };
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calState <= 1;
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end
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else if (calState == 1) begin
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average <= average + {8'b0, blue_total};
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calState <= 2;
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end
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else if (calState == 2) begin
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average <= average << 8;
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calState <= 3;
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end
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else if (calState == 3) begin
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r_white_gain[0] <= average / {8'b0, red_total};
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r_white_gain[1] <= average / {8'b0, green_total};
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r_white_gain[2] <= average / {8'b0, blue_total};
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isCal <= 0;
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calState <= 4;
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end
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else if (calState == 4) begin
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data_cal[0] <= (data_cache[0] * r_white_gain[0][31:0]);
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data_cal[1] <= (data_cache[1] * r_white_gain[1][31:0]);
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data_cal[2] <= (data_cache[2] * r_white_gain[2][31:0]);
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calState <= 5;
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end
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else begin
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calState <= isCal ? 0 : 4;
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end
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end
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SEND_DATA: begin
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if (in_ready) begin
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out_en <= 1;
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if (enable) begin
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out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
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out_data[1] <= (|data_cal[1][31:16]) ? 255 : (data_cal[1] > 0 ? data_cal[1][15:8] : 0);
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out_data[2] <= (|data_cal[2][31:16]) ? 255 : (data_cal[2] > 0 ? data_cal[2][15:8] : 0);
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end else begin
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out_data[0] <= data_cache[0][7:0];
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out_data[1] <= data_cache[1][7:0];
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out_data[2] <= data_cache[2][7:0];
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end
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end else out_en <= 0;
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end
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default: ;
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endcase
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end
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end
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endmodule
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163
rtl/Color/SaturationCorrection.sv
Executable file
163
rtl/Color/SaturationCorrection.sv
Executable file
@@ -0,0 +1,163 @@
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`timescale 1ns / 1ps
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module SaturationCorrection #(
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parameter reg [4:0] COLOR_DEPTH = 8
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) (
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input wire clk,
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input wire reset,
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input wire in_en,
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input wire [COLOR_DEPTH - 1 : 0] in_data[3],
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output wire out_ready,
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output wire out_receive,
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output reg out_en,
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output reg [COLOR_DEPTH - 1 : 0] out_data[3],
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input wire in_ready,
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input wire in_receive,
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input wire enable,
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input wire signed [31:0] saturation_inc
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);
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reg [2:0] state, nextState, calState;
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localparam reg [2:0] READ_DATA = 0;
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localparam reg [2:0] CALC_DATA = 1;
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localparam reg [2:0] SEND_DATA = 2;
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reg signed [31:0] data_cal[3], data_cache[3];
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// wire signed [31:0] max, min, delta, value, light, saturation, alpha;
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reg signed [31:0] max, min, delta, value, light, saturation, alpha;
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always @(posedge clk) begin
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if (reset) state <= READ_DATA;
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else state <= nextState;
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end
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always @(*) begin
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case (state)
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READ_DATA: nextState = in_en ? 3 : READ_DATA;
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3: nextState = CALC_DATA;
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CALC_DATA: nextState = (calState >= 5 || !enable) ? SEND_DATA : CALC_DATA;
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SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
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default: nextState = READ_DATA;
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endcase
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end
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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// assign max = data_cache[0] > data_cache[1]?
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// (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
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// (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
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// assign min = data_cache[0] < data_cache[1]?
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// (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
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// (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
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// assign delta = max - min;
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// assign value = max + min;
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// assign light = value >>> 1;
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// // // assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value);
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// assign saturation = (delta <<< 8) / max;
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// assign alpha = (saturation_inc[31] == 0)
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// ? ((saturation_inc + saturation >= 256)
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// ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
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// : (saturation_inc);
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always @(posedge clk) begin
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if (reset) begin
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calState <= 0;
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out_en <= 0;
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out_data[0] <= 0;
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out_data[1] <= 0;
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out_data[2] <= 0;
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min <= 0;
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max <= 0;
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delta <= 0;
|
||||
value <= 0;
|
||||
light <= 0;
|
||||
saturation <= 0;
|
||||
alpha <= 0;
|
||||
|
||||
data_cal[0] <= 0;
|
||||
data_cal[1] <= 0;
|
||||
data_cal[2] <= 0;
|
||||
data_cache[0] <= 0;
|
||||
data_cache[1] <= 0;
|
||||
data_cache[2] <= 0;
|
||||
end else begin
|
||||
case (state)
|
||||
READ_DATA: begin
|
||||
if (in_en) begin
|
||||
data_cache[0] <= {24'b0, in_data[0]};
|
||||
data_cache[1] <= {24'b0, in_data[1]};
|
||||
data_cache[2] <= {24'b0, in_data[2]};
|
||||
end
|
||||
end
|
||||
|
||||
CALC_DATA: begin
|
||||
if (enable) begin
|
||||
if (calState == 0) begin
|
||||
max <= data_cache[0] > data_cache[1]?
|
||||
(data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
|
||||
(data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
|
||||
min <= data_cache[0] < data_cache[1]?
|
||||
(data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
|
||||
(data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
|
||||
|
||||
calState <= 1;
|
||||
end else if (calState == 1) begin
|
||||
delta <= max - min;
|
||||
value <= max + min;
|
||||
|
||||
calState <= 2;
|
||||
end else if (calState == 2) begin
|
||||
light <= value >>> 1;
|
||||
saturation <= (delta <<< 8) / max;
|
||||
|
||||
calState <= 3;
|
||||
end else if (calState == 3) begin
|
||||
alpha <= (saturation_inc[31] == 0) ? ((saturation_inc + saturation >= 255)
|
||||
? (65536 / saturation) - 255 : (65536 / (256 - saturation_inc)) - 255)
|
||||
: (saturation_inc);
|
||||
|
||||
calState <= 4;
|
||||
end else if (calState == 4) begin
|
||||
if (saturation_inc[31] == 0) begin
|
||||
data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha);
|
||||
data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha);
|
||||
data_cal[2] <= (data_cache[2] << 8) + ((data_cache[2] - light) * alpha);
|
||||
end else begin
|
||||
data_cal[0] <= (light << 8) + (data_cache[0] - light) * (256 + alpha);
|
||||
data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha);
|
||||
data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha);
|
||||
end
|
||||
|
||||
calState <= 5;
|
||||
end else begin
|
||||
calState <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
SEND_DATA: begin
|
||||
if (in_ready && !in_receive) begin
|
||||
out_en <= 1;
|
||||
if (enable && delta != 0) begin
|
||||
out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
|
||||
out_data[1] <= (|data_cal[1][31:16]) ? 255 : (data_cal[1] > 0 ? data_cal[1][15:8] : 0);
|
||||
out_data[2] <= (|data_cal[2][31:16]) ? 255 : (data_cal[2] > 0 ? data_cal[2][15:8] : 0);
|
||||
end else begin
|
||||
out_data[0] <= data_cache[0][7:0];
|
||||
out_data[1] <= data_cache[1][7:0];
|
||||
out_data[2] <= data_cache[2][7:0];
|
||||
end
|
||||
end else out_en <= 0;
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
135
rtl/Color/WhiteBalance.sv
Executable file
135
rtl/Color/WhiteBalance.sv
Executable file
@@ -0,0 +1,135 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// 三通道图像合成一个RGB图像
|
||||
module WhiteBalance #(
|
||||
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
|
||||
parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
|
||||
parameter reg [8:0] BUFF_SIZE = 32,
|
||||
parameter reg [31:0] RAM_BEGIN_ADDR = 0,
|
||||
parameter reg [31:0] IM_SIZE = 1920 * 1080
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
input wire in_en,
|
||||
input wire [15:0] in_data[3], // 0:R 1:G 2:B
|
||||
output wire out_ready,
|
||||
output wire out_receive,
|
||||
|
||||
// 输出相关
|
||||
input wire in_ready,
|
||||
input wire in_receive,
|
||||
output wire out_en,
|
||||
output wire [OUT_DEPTH - 1:0] out_data[3],
|
||||
|
||||
input wire enable,
|
||||
input wire [8:0] flame_rate,
|
||||
input wire [31:0] white_gain[3]
|
||||
);
|
||||
|
||||
wire ram_read_en, ram_write_en, ram_read_ready, ram_write_ready;
|
||||
wire [31:0] ram_read_data, ram_read_addr, ram_write_data, ram_write_addr;
|
||||
|
||||
reg [8:0] cnt_flame;
|
||||
reg [31:0] cnt_in_pic, cnt_out_pic, cnt_pixels;
|
||||
reg [31:0] red_total, green_total, blue_total;
|
||||
reg [31:0] r_white_gain[3];
|
||||
|
||||
wire is_finish_cal;
|
||||
always @(*) begin
|
||||
if (cnt_in_pic >= IM_SIZE) is_finish_cal = 1;
|
||||
else if (cnt_out_pic >= IM_SIZE) is_finish_cal = 0;
|
||||
else is_finish_cal = is_finish_cal;
|
||||
end
|
||||
|
||||
assign ram_read_addr = cnt_out_pic;
|
||||
assign ram_write_addr = cnt_in_pic;
|
||||
assign cnt_pixels = (is_finish_cal)
|
||||
? IM_SIZE - cnt_out_pic + cnt_in_pic
|
||||
: cnt_in_pic - cnt_out_pic;
|
||||
|
||||
assign out_ready = (!in_en && !reset && cnt_pixels < IM_SIZE) ? 1 : 0;
|
||||
assign out_receive = (in_en && !reset && cnt_in_pic < IM_SIZE) ? 1 : 0;
|
||||
|
||||
DiffWidthSyncFIFO #(
|
||||
.DATA_WIDTH (8),
|
||||
.DATA_DEPTH (12),
|
||||
.READ_DEPTH (4),
|
||||
.WRITE_DEPTH(3)
|
||||
) in_fifo (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.read_ready(ram_write_ready),
|
||||
.read_en(ram_write_en),
|
||||
.read_data(ram_write_data),
|
||||
.write_ready(in_ready),
|
||||
.write_en(in_en),
|
||||
.write_data(in_data)
|
||||
);
|
||||
|
||||
DiffWidthSyncFIFO #(
|
||||
.DATA_WIDTH (8),
|
||||
.DATA_DEPTH (12),
|
||||
.READ_DEPTH (3),
|
||||
.WRITE_DEPTH(4)
|
||||
) out_fifo (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.read_ready(out_ready),
|
||||
.read_en(out_en),
|
||||
.read_data(out_data),
|
||||
.write_ready(ram_read_ready),
|
||||
.write_en(ram_read_en),
|
||||
.write_data(ram_read_data)
|
||||
);
|
||||
|
||||
SDRAM inst_RAM (
|
||||
.clk(clk),
|
||||
.read_en(ram_read_en),
|
||||
.read_addr(ram_read_addr),
|
||||
.read_data(ram_read_data),
|
||||
.read_ready(ram_read_ready),
|
||||
.write_en(ram_write_en),
|
||||
.write_addr(ram_write_addr),
|
||||
.write_data(ram_write_data),
|
||||
.write_ready(ram_write_ready)
|
||||
);
|
||||
|
||||
// calculate white gain
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
red_total <= 0;
|
||||
green_total <= 0;
|
||||
blue_total <= 0;
|
||||
cnt_flame <= 0;
|
||||
cnt_in_pic <= 0;
|
||||
r_white_gain[0] <= white_gain[0];
|
||||
r_white_gain[1] <= white_gain[1];
|
||||
r_white_gain[2] <= white_gain[2];
|
||||
end else begin
|
||||
if (in_en && cnt_pixels < IM_SIZE) begin
|
||||
red_total <= red_total + in_data[0];
|
||||
green_total <= green_total + in_data[1];
|
||||
blue_total <= blue_total + in_data[2];
|
||||
if (cnt_in_pic < IM_SIZE) cnt_in_pic <= cnt_in_pic + 1;
|
||||
else cnt_in_pic <= 0;
|
||||
end else begin
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// calculate out data
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
cnt_out_pic <= 0;
|
||||
end else begin
|
||||
if (out_ready && is_finish_cal) begin
|
||||
out_en <= 1;
|
||||
end else begin
|
||||
out_en <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user