just make a little part of saturation correction

This commit is contained in:
SikongJueluo
2024-06-29 21:31:58 +08:00
parent 24ac284c52
commit 7833c3a7b5
3 changed files with 142 additions and 9 deletions

View File

@@ -0,0 +1,97 @@
`timescale 1ns / 1ps
module SaturationCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
output wire out_ready,
output wire out_receive,
output reg out_en,
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
input wire in_ready,
input wire in_receive,
input wire enable,
input wire [8:0] saturation_inc
);
reg [2:0] state, nextState;
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SEND_DATA = 2;
reg [15:0] data_cal[3];
always @(posedge clk or posedge reset) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
always @(*) begin
case (state)
READ_DATA: nextState = in_en ? CALC_DATA : READ_DATA;
CALC_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
assign max = data_cal[0] > data_cal[1]?
(data_cal[0] > data_cal[2] ? data_cal[0] : data_cal[2]):
(data_cal[1] > data_cal[2] ? data_cal[1] : data_cal[2]);
assign min = data_cal[0] < data_cal[1]?
(data_cal[0] < data_cal[2] ? data_cal[0] : data_cal[2]):
(data_cal[1] < data_cal[2] ? data_cal[1] : data_cal[2]);
assign delta = max - min;
assign value = max + min;
assign light = value >> 1;
assign saturation = (delta << 8) / max;
always @(posedge clk or posedge reset) begin
if (reset) begin
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
data_cal[0] <= 0;
data_cal[1] <= 0;
data_cal[2] <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
end
end
CALC_DATA: begin
if (enable) begin
end
end
SEND_DATA: begin
if (in_ready) begin
out_en <= 1;
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule