change a little

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SikongJueluo 2024-07-02 21:59:39 +08:00
parent 4dffc45257
commit 649d34415f
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10 changed files with 40 additions and 95 deletions

39
Color/WhiteBalance.sv Normal file
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@ -0,0 +1,39 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module WhiteBalance #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
parameter reg [8:0] BUFF_SIZE = 32
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [15:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [OUT_DEPTH - 1:0] out_data[3],
input wire enable,
input wire [8:0] flame_rate
);
assign out_ready = (!reset) ? 1 : 0;
assign out_receive = (in_en && !reset) ? 1 : 0;
DiffWidthSyncFIFO #(
)
always @(posedge clk) begin
if(reset) begin
end
end
endmodule

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@ -1,94 +0,0 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module WhiteBalance #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
parameter reg [8:0] BUFF_SIZE = 32
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [15:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [OUT_DEPTH - 1:0] out_data[3]
);
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SATI_DATA = 2;
localparam reg [2:0] SEND_DATA = 3;
reg [2:0] state, nextState;
reg [BUFF_SIZE - 1:0] data_cal[3]; // 用于保存运算结果防止溢出
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= READ_DATA;
end else begin
state <= nextState;
end
end
always @(*) begin
case (state)
READ_DATA: nextState = (in_en) ? CALC_DATA : READ_DATA;
CALC_DATA: nextState = SATI_DATA;
SATI_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = (in_receive) ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
// 初始化
data_cal[0] <= 0;
data_cal[1] <= 0;
data_cal[2] <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
out_en <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
end
end
CALC_DATA: begin
if (enable) begin
end
end
SATI_DATA: begin
end
SEND_DATA: begin
if (in_ready && !in_receive) begin
out_en <= 1;
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule

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@ -56,7 +56,7 @@ VERILATOR_FLAGS += --threads 14
TOP_MODULE = isp TOP_MODULE = isp
VERILATOR_FLAGS += -top $(TOP_MODULE) VERILATOR_FLAGS += -top $(TOP_MODULE)
# Input files for Verilator # Input files for Verilator
VERILATOR_INPUT = ../isp.v *.cpp ../Demosaic/Demosaic2.v ../Crop/*.v ../Color/*.v ../RAM/*.v VERILATOR_INPUT = ../isp.sv *.cpp ../Demosaic/Demosaic2.sv ../Crop/*.sv ../Color/*.sv ../RAM/*.sv
# Check if SC exists via a verilator call (empty if not) # Check if SC exists via a verilator call (empty if not)
SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC) SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)