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fix DPC and reconstruct isp

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SikongJueluo
2024-11-03 20:38:29 +08:00
parent a8fa609228
commit 42f6cdbbda
41 changed files with 25742 additions and 693 deletions
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1
rtl/Crop/Crop.sv
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@@ -1,4 +1,3 @@
`timescale 1ns/1ps
module Crop #(
parameter reg [15:0] IN_WIDTH = 1934,
parameter reg [15:0] IN_HEIGHT = 1086,

109
rtl/Crop/Crop_Pipeline.sv
View File

@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
module Crop_Pipeline #(
parameter IN_WIDTH = 512,
parameter IN_HEIGHT = 512,
@@ -14,89 +13,101 @@ module Crop_Pipeline #(
input wire clk,
input wire reset,
input wire [COLOR_DEPTH - 1:0] in_data [3],
output reg [COLOR_DEPTH - 1:0] out_data[3],
input wire [COLOR_DEPTH - 1:0] in_data [3],
input wire [7:0] in_user,
output reg [COLOR_DEPTH - 1:0] out_data [3],
output wire [7:0] out_user,
input wire in_valid,
output reg out_valid,
input wire in_valid,
output reg out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output reg out_hsync,
output reg out_fsync
input wire in_ready,
output wire out_ready
);
localparam PIPILINE = 3;
wire in_fstart, in_hstart;
reg out_fstart, out_hstart;
assign in_fstart = in_user[1];
assign in_hstart = in_user[0];
reg [PIPILINE-1:0] pipeline_valid;
localparam PIPELINE = 3;
reg [5:0] pipeline_user[PIPELINE];
reg [PIPELINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
assign pipeline_running = in_ready | ~pipeline_valid[PIPELINE-1];
reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
reg force_dis, force_en;
reg force_dis;
reg [COLOR_DEPTH-1:0] data_cache0[3];
reg [COLOR_DEPTH-1:0] data_cache1[3];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid[PIPILINE-1] & ~force_dis) | force_en;
assign out_valid = (pipeline_valid[PIPELINE-1] & ~force_dis);
assign out_user = {pipeline_user[PIPELINE-1],out_fstart,out_hstart};
//分别表示当前像素: 显示；被裁掉；空。
reg [1:0] flag_crop;
localparam CROP_ERROR = 2'b00, CROP_KEEP = 2'b01, CROP_GIVE_UP = 2'b10, CROP_BLANK = 2'b11;
reg flag_crop;
localparam CROP_KEEP = 1'b0,
CROP_GIVE_UP = 1'b1;
integer i;
always @(posedge clk) begin
if (reset) begin
if(reset) for(i=0;i<3;i=i+1) data_cache0[i] <= 0;
else if(pipeline_running & in_valid) for(i=0;i<3;i++) data_cache0[i] <= in_data[i];
else for(i=0;i<3;i=i+1) data_cache0[i] <= data_cache0[i];
end
always @(posedge clk) begin
if(reset) for(i=0;i<3;i=i+1) data_cache1[i] <= 0;
else if(pipeline_running & pipeline_valid[0]) for(i=0;i<3;i++) data_cache1[i] <= data_cache0[i];
else for(i=0;i<3;i=i+1) data_cache1[i] <= data_cache1[i];
end
always @(posedge clk) begin
if(reset) begin
pipeline_valid <= 0;
cnt_x <= 0;
cnt_y <= 0;
for (i = 0; i < 3; i++) data_cache0[i] <= 0;
for (i = 0; i < 3; i++) data_cache1[i] <= 0;
for (i = 0; i < 3; i++) out_data[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
flag_crop <= 0;
force_dis <= 0;
force_en <= 0;
out_hsync <= 0;
out_fsync <= 0;
out_hstart <= 0;
out_fstart <= 0;
temp_x <= 0;
temp_y <= 0;
end else if (pipeline_running) begin
for(i=0;i<PIPELINE;i=i+1) pipeline_user[i] <= 0;
end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
pipeline_valid <= {pipeline_valid[PIPELINE-2:0],in_valid};
if (in_valid) begin //when 00
for (i = 0; i < 3; i++) data_cache0[i] <= in_data[i];
cnt_x <= (in_hsync) ? (0) : (cnt_x + 1);
cnt_y <= (in_hsync) ? ((in_fsync) ? (0) : (cnt_y + 1)) : (cnt_y);
if(in_valid) begin //when 00
pipeline_user[0] <= in_user[7:2];
cnt_x <= (in_hstart)?(0):(cnt_x+1);
cnt_y <= (in_hstart)?((in_fstart)?(0):(cnt_y+1)):(cnt_y);
end
if (pipeline_valid[0]) begin //when 00
for (i = 0; i < 3; i++) data_cache1[i] <= data_cache0[i];
if(pipeline_valid[0]) begin //when 00
pipeline_user[1] <= pipeline_user[0];
temp_x <= cnt_x;
temp_y <= cnt_y;
if (cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
else if (cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) begin
if (cnt_x < IN_WIDTH && cnt_y < IN_HEIGHT) flag_crop <= CROP_KEEP;
else flag_crop <= CROP_BLANK;
end else flag_crop <= CROP_ERROR;
if(cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
else if(cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) flag_crop <= CROP_KEEP;
else flag_crop <= CROP_GIVE_UP;
end
if (pipeline_valid[1]) begin
for (i = 0; i < 3; i++) out_data[i] <= data_cache1[i];
out_hsync <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
out_fsync <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
if(pipeline_valid[1]) begin
pipeline_user[2] <= pipeline_user[1];
for(i=0;i<3;i++) out_data[i] <= data_cache1[i];
out_hstart <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
out_fstart <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
case (flag_crop)
CROP_ERROR: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_KEEP: {force_dis, force_en} <= {1'b0, 1'b0};
CROP_GIVE_UP: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_BLANK:
{force_dis, force_en} <= {1'b0, 1'b0}; //应该是01, 但我还没写BLANK逻辑
CROP_KEEP : force_dis <= 1'b0;
CROP_GIVE_UP : force_dis <= 1'b1;
endcase
end
end