SikongJueluo/ISP
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

use cmake to replace makefiel

Browse Source
This commit is contained in:
SikongJueluo
2024-10-03 15:13:24 +08:00
parent 7e12105a3d
commit 35e6ab1e85
24 changed files with 1887 additions and 882 deletions
Download Patch File Download Diff File Expand all files Collapse all files

162
rtl/Color/ColorBlender.sv
View File

@@ -1,5 +1,4 @@
`timescale 1ns / 1ps
`timescale 1ns/1ps
// 三通道图像合成一个RGB图像
module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
@@ -7,21 +6,17 @@ module ColorBlender #(
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
input wire in_en,
input wire [15:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [OUT_DEPTH - 1:0] out_data[3],
// 颜色校正
input wire [15:0] gain_red,
@@ -29,70 +24,85 @@ module ColorBlender #(
input wire [15:0] gain_blue,
input wire enable
);
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SATI_DATA = 2;
localparam reg [2:0] SEND_DATA = 3;
localparam PIPELINE = 4;
reg [2:0] state, nextState;
reg [32 - 1:0] data_cal[3]; // 用于保存运算结果，防止溢出
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3];
reg [32 - 1:0] data_cal2[3];
integer i;
always @(posedge clk) begin
if(reset) begin
pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
end else if(pipeline_flag) begin
/************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;
data_cal1[2] <= data_cal0[2] >> 8;
if (reset) begin
state <= READ_DATA;
end else begin
state <= nextState;
end
end
always @(*) begin
case (state)
READ_DATA: nextState = (in_en) ? CALC_DATA : READ_DATA;
CALC_DATA: nextState = SATI_DATA;
SATI_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = (in_receive) ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk) begin
if (reset) begin
// 初始化
data_cal[0] <= 0;
data_cal[1] <= 0;
data_cal[2] <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
out_en <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data_cal[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
end
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
end
CALC_DATA: begin
if (enable) begin
data_cal[0] <= (data_cal[0] * {16'b0, gain_red}) >> 16;
data_cal[1] <= (data_cal[1] * {16'b0, gain_green}) >> 16;
data_cal[2] <= (data_cal[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal[0] <= data_cal[0] >> 8;
data_cal[1] <= data_cal[1] >> 8;
data_cal[2] <= data_cal[2] >> 8;
end
end
SATI_DATA: begin
data_cal[0] <= |data_cal[0][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[0];
data_cal[1] <= |data_cal[1][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[1];
data_cal[2] <= |data_cal[2][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[2];
end
SEND_DATA: begin
if (in_ready && !in_receive) begin
out_en <= 1;
out_data[0] <= data_cal[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal[2][OUT_DEPTH-1:0];
end else out_en <= 0;
end
default: ;
endcase
end
end

99
rtl/Color/ColorBlender_Pipeline.sv Normal file
View File

@@ -0,0 +1,99 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
// 颜色校正
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire enable
);
localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3];
reg [32 - 1:0] data_cal2[3];
integer i;
always @(posedge clk) begin
if(reset) begin
pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
end else if(pipeline_flag) begin
/************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;
data_cal1[2] <= data_cal0[2] >> 8;
end
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
end
end
end
endmodule

210
rtl/Crop/Crop.sv
View File

@@ -1,106 +1,104 @@
`timescale 1ns / 1ps
module Crop #(
parameter IN_WIDTH = 512,
parameter IN_HEIGHT = 512,
parameter OFFSET_X = 120,
parameter OFFSET_Y = 256,
// parameter TRANSLAYT_X = 120,
// parameter TRANSLAYT_Y = 120,
parameter OUT_WIDTH = 512,
parameter OUT_HEIGHT = 512,
parameter BLANK_COLOR = 6'h000000,
parameter COLOR_DEPTH = 16
) (
input wire clk,
input wire reset,
input wire [COLOR_DEPTH - 1:0] in_data [3],
output reg [COLOR_DEPTH - 1:0] out_data[3],
input wire in_valid,
output reg out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output reg out_hsync,
output reg out_fsync
);
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
reg force_dis, force_en;
reg [COLOR_DEPTH-1:0] data_cache0[3];
reg [COLOR_DEPTH-1:0] data_cache1[3];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid[PIPILINE-1] & ~force_dis) | force_en;
//分别表示当前像素: 显示；被裁掉；空。
reg [1:0] flag_crop;
localparam CROP_ERROR = 2'b00, CROP_KEEP = 2'b01, CROP_GIVE_UP = 2'b10, CROP_BLANK = 2'b11;
integer i;
always @(posedge clk) begin
if (reset) begin
pipeline_valid <= 0;
cnt_x <= 0;
cnt_y <= 0;
for (i = 0; i < 3; i++) data_cache0[i] <= 0;
for (i = 0; i < 3; i++) data_cache1[i] <= 0;
for (i = 0; i < 3; i++) out_data[i] <= 0;
flag_crop <= 0;
force_dis <= 0;
force_en <= 0;
out_hsync <= 0;
out_fsync <= 0;
temp_x <= 0;
temp_y <= 0;
end else if (pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin //when 00
for (i = 0; i < 3; i++) data_cache0[i] <= in_data[i];
cnt_x <= (in_hsync) ? (0) : (cnt_x + 1);
cnt_y <= (in_hsync) ? ((in_fsync) ? (0) : (cnt_y + 1)) : (cnt_y);
end
if (pipeline_valid[0]) begin //when 00
for (i = 0; i < 3; i++) data_cache1[i] <= data_cache0[i];
temp_x <= cnt_x;
temp_y <= cnt_y;
if (cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
else if (cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) begin
if (cnt_x < IN_WIDTH && cnt_y < IN_HEIGHT) flag_crop <= CROP_KEEP;
else flag_crop <= CROP_BLANK;
end else flag_crop <= CROP_ERROR;
end
if (pipeline_valid[1]) begin
for (i = 0; i < 3; i++) out_data[i] <= data_cache1[i];
out_hsync <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
out_fsync <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
case (flag_crop)
CROP_ERROR: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_KEEP: {force_dis, force_en} <= {1'b0, 1'b0};
CROP_GIVE_UP: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_BLANK:
{force_dis, force_en} <= {1'b0, 1'b0}; //应该是01, 但我还没写BLANK逻辑
endcase
end
end
end
endmodule
`timescale 1ns/1ps
module Crop #(
parameter reg [15:0] IN_WIDTH = 1934,
parameter reg [15:0] IN_HEIGHT = 1086,
parameter reg [15:0] OFFSET_X = 7,
parameter reg [15:0] OFFSET_Y = 3,
parameter reg [15:0] OUT_WIDTH = 640,
parameter reg [15:0] OUT_HEIGHT = 480,
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_en,
output wire out_ready,
output wire out_receive,
input wire [COLOR_DEPTH - 1:0] in_data[3],
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [COLOR_DEPTH - 1:0] out_data[3]
);
reg [1:0] state, nextState;
localparam reg [1:0] READ_DATA = 0;
localparam reg [1:0] HANDLE_DATA = 1;
localparam reg [1:0] SEND_DATA = 2;
reg [15:0] cnt_x, cnt_y;
reg [COLOR_DEPTH - 1:0] data[3];
wire is_valid;
// 状态切换
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
// 下一状态更新
always @(*) begin
case (state)
READ_DATA: nextState = in_en ? HANDLE_DATA : READ_DATA;
HANDLE_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = (is_valid && !in_receive) ? SEND_DATA : READ_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) &&
(OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0;
always @(posedge clk) begin
if (reset) begin
cnt_x <= 0;
cnt_y <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data[0] <= in_data[0];
data[1] <= in_data[1];
data[2] <= in_data[2];
end
end
HANDLE_DATA: begin
if (cnt_x >= IN_WIDTH - 1) begin
cnt_x <= 0;
cnt_y <= cnt_y + 1;
end else begin
cnt_x <= cnt_x + 1;
end
end
SEND_DATA: begin
if (cnt_y >= IN_HEIGHT) begin
cnt_y <= 0;
end
if (in_ready && !in_receive && is_valid) begin
out_en <= 1;
out_data[0] <= data[0];
out_data[1] <= data[1];
out_data[2] <= data[2];
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule

106
rtl/Crop/Crop_Pipeline.sv Normal file
View File

@@ -0,0 +1,106 @@
`timescale 1ns / 1ps
module Crop #(
parameter IN_WIDTH = 512,
parameter IN_HEIGHT = 512,
parameter OFFSET_X = 120,
parameter OFFSET_Y = 256,
// parameter TRANSLAYT_X = 120,
// parameter TRANSLAYT_Y = 120,
parameter OUT_WIDTH = 512,
parameter OUT_HEIGHT = 512,
parameter BLANK_COLOR = 6'h000000,
parameter COLOR_DEPTH = 16
) (
input wire clk,
input wire reset,
input wire [COLOR_DEPTH - 1:0] in_data [3],
output reg [COLOR_DEPTH - 1:0] out_data[3],
input wire in_valid,
output reg out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output reg out_hsync,
output reg out_fsync
);
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
reg force_dis, force_en;
reg [COLOR_DEPTH-1:0] data_cache0[3];
reg [COLOR_DEPTH-1:0] data_cache1[3];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid[PIPILINE-1] & ~force_dis) | force_en;
//分别表示当前像素: 显示；被裁掉；空。
reg [1:0] flag_crop;
localparam CROP_ERROR = 2'b00, CROP_KEEP = 2'b01, CROP_GIVE_UP = 2'b10, CROP_BLANK = 2'b11;
integer i;
always @(posedge clk) begin
if (reset) begin
pipeline_valid <= 0;
cnt_x <= 0;
cnt_y <= 0;
for (i = 0; i < 3; i++) data_cache0[i] <= 0;
for (i = 0; i < 3; i++) data_cache1[i] <= 0;
for (i = 0; i < 3; i++) out_data[i] <= 0;
flag_crop <= 0;
force_dis <= 0;
force_en <= 0;
out_hsync <= 0;
out_fsync <= 0;
temp_x <= 0;
temp_y <= 0;
end else if (pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin //when 00
for (i = 0; i < 3; i++) data_cache0[i] <= in_data[i];
cnt_x <= (in_hsync) ? (0) : (cnt_x + 1);
cnt_y <= (in_hsync) ? ((in_fsync) ? (0) : (cnt_y + 1)) : (cnt_y);
end
if (pipeline_valid[0]) begin //when 00
for (i = 0; i < 3; i++) data_cache1[i] <= data_cache0[i];
temp_x <= cnt_x;
temp_y <= cnt_y;
if (cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
else if (cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) begin
if (cnt_x < IN_WIDTH && cnt_y < IN_HEIGHT) flag_crop <= CROP_KEEP;
else flag_crop <= CROP_BLANK;
end else flag_crop <= CROP_ERROR;
end
if (pipeline_valid[1]) begin
for (i = 0; i < 3; i++) out_data[i] <= data_cache1[i];
out_hsync <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
out_fsync <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
case (flag_crop)
CROP_ERROR: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_KEEP: {force_dis, force_en} <= {1'b0, 1'b0};
CROP_GIVE_UP: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_BLANK:
{force_dis, force_en} <= {1'b0, 1'b0}; //应该是01, 但我还没写BLANK逻辑
endcase
end
end
end
endmodule

187
rtl/Demosaic/Demosaic2.sv Normal file
View File

@@ -0,0 +1,187 @@
`timescale 1ns/1ps
module Demosaic2 #(
parameter reg [15:0] IM_WIDTH = 512, // 图像宽度
parameter reg [15:0] IM_HEIGHT = 256, // 图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // 0:grbg 1:rggb 2:bggr 3:gbrg
parameter reg [ 4:0] DATA_SIZE = 16
) (
// 基本信号
input wire clk,
input wire reset,
// 数据输入信号
input wire in_en,
input wire [DATA_SIZE - 1:0] in_data [3], // 数据输入线，0、1、2分别表示第一、二、三行
output wire out_ready, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
output wire out_receive,
// en: 输出数据有效信号，高电平有效
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [DATA_SIZE - 1:0] out_r,
output reg [DATA_SIZE - 1:0] out_g,
output reg [DATA_SIZE - 1:0] out_b
);
// 常量，包括状态机
// localparam IM_SIZE = IM_HEIGHT * IM_WIDTH;
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] COLOR_GEN = 1;
localparam reg [2:0] SEND_DATA = 2;
localparam reg [2:0] SLIDE_WINDOW = 3;
// 寄存器
reg [2:0] state, nextState;
reg [15:0] data_cache[9]; // 缓存颜色数据，行列3x3
reg [15:0] pos_x, pos_y; // 滑动窗口左上角位置
reg [2:0] cnt_data; // 记录输入数据数量，最大值256
reg [1:0] raw_type;
reg [15:0] red, blue, green;
// 三段状态机实现，窗口滑动，颜色计算
// 状态切换
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
// 下一状态更新
always @(*) begin
case (state)
// 记录够3x3个数据后，进行rgb转换
READ_DATA: nextState = (cnt_data >= 3) ? COLOR_GEN : READ_DATA;
COLOR_GEN: nextState = SEND_DATA;
SEND_DATA: nextState = (in_receive) ? SLIDE_WINDOW : SEND_DATA;
SLIDE_WINDOW: nextState = READ_DATA;
default: nextState = READ_DATA;
endcase
end
// 请求数据
assign out_ready = (cnt_data <= 2 && !in_en && state == READ_DATA && !reset) ? 1 : 0;
// 收到数据
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
// 各状态执行的操作
always @(posedge clk) begin
if (reset) begin
// 外部输出初始化
out_en <= 0;
out_r <= 0;
out_g <= 0;
out_r <= 0;
// 内部寄存器初始化
pos_x <= 0;
pos_y <= 0;
cnt_data <= 0;
raw_type <= RAW_TYPE;
end else begin
// 状态机执行
case (state)
// 读取数据
READ_DATA: begin
if (in_en) begin
data_cache[0 + cnt_data * 3] <= in_data[0];
data_cache[1 + cnt_data * 3] <= in_data[1];
data_cache[2 + cnt_data * 3] <= in_data[2];
cnt_data <= cnt_data + 1;
end
end
COLOR_GEN: begin
// 生成rgb图像
// data case 0 case 1 case 2 case 3
// 0 3 6 G R G R G R B G B G B G
// 1 4 7 B G B G B G G R G R G R
// 2 5 8 G R G R G R B G B G B G
case (raw_type)
0: begin // Missing B, R on G
blue <= (data_cache[1] + data_cache[7]) >> 1;
red <= (data_cache[3] + data_cache[5]) >> 1;
green <= data_cache[4];
end
1: begin // Missing G, R on B
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
red <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
blue <= data_cache[4];
end
2: begin // Missing G, B on R
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
blue <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
red <= data_cache[4];
end
3: begin // Missing B, R on G
red <= (data_cache[1] + data_cache[7]) >> 1;
blue <= (data_cache[3] + data_cache[5]) >> 1;
green <= data_cache[4];
end
default: ;
endcase
case (raw_type)
0: raw_type <= 1;
1: raw_type <= 0;
2: raw_type <= 3;
3: raw_type <= 2;
endcase
end
SEND_DATA: begin
if (in_ready && !in_receive) begin
out_en <= 1;
out_r <= red;
out_b <= blue;
out_g <= green;
end else out_en <= 0;
end
SLIDE_WINDOW: begin
// 记录位置寄存器自增，并处理缓存数据
pos_x <= pos_x + 1;
if (pos_x >= IM_WIDTH - 2 - 1) begin
cnt_data <= 0;
pos_x <= 0;
pos_y <= pos_y + 1;
if (pos_y >= IM_HEIGHT - 2 - 1) begin
pos_y <= 0;
end
// 换行后切换Bayer格式
if (pos_y % 2 == 1) begin
raw_type <= RAW_TYPE;
end else begin
case (RAW_TYPE)
0: raw_type <= 2;
1: raw_type <= 3;
2: raw_type <= 0;
3: raw_type <= 1;
default: ;
endcase
end
end else begin
cnt_data <= 2;
// 窗口右移
data_cache[0] <= data_cache[3];
data_cache[1] <= data_cache[4];
data_cache[2] <= data_cache[5];
data_cache[3] <= data_cache[6];
data_cache[4] <= data_cache[7];
data_cache[5] <= data_cache[8];
end
end
default: ;
endcase
end
end
endmodule

0
rtl/Demosaic/Demosaic.sv → rtl/Demosaic/Demosaic_Pipeline.sv
View File

0
rtl/Windows.sv → rtl/Demosaic/Windows.sv
View File

359
rtl/isp.sv
View File

@@ -1,153 +1,206 @@
`timescale 1ns / 1ps
module isp #(
parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088,
parameter OFFSET_X = 7,
parameter OFFSET_Y = 3,
parameter reg [15:0] OUT_WIDTH = 1920,
parameter reg [15:0] OUT_HEIGHT = 1080,
parameter reg [ 4:0] COLOR_DEPTH = 8, // Can't Change!!!
parameter reg [ 1:0] RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
) (
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [15:0] in_data[3], // 数据输入线，0、1、2分别表示第一、二、三行
output wire [3 * COLOR_DEPTH - 1:0] out_data,
// 数据有效信号
input wire in_valid,
output wire out_valid,
// 准备信号
input wire in_ready,
output wire out_ready,
// 颜色校正，低八位为小数位，高八位为整数位
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire blender_enable // 是否启用颜色校正
);
wire [15:0] Demosaic2_data[3];
wire [15:0] Windows_data[9];
wire [COLOR_DEPTH - 1 : 0] Blender_data[3];
wire [COLOR_DEPTH - 1 : 0] Crop_data[3];
wire Windows_valid, Demosaic2_valid, Blender_valid, Crop_valid;
wire Windows_ready, Demosaic2_ready, Blender_ready, Crop_ready;
wire Demosaic2_hsync, Blender_hsync, Crop_hsync;
wire Demosaic2_fsync, Blender_fsync, Crop_fsync;
assign out_valid = Crop_valid;
assign out_ready = Windows_ready;
assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]};
Windows #(
.DATA_WIDTH(16)
) Windows_inst (
.clk (clk),
.reset (reset),
.in_data (in_data),
.out_data (Windows_data),
.in_valid (in_valid),
.out_valid(Windows_valid),
.in_ready (Demosaic2_ready),
.out_ready(Windows_ready)
);
Demosaic #(
.WINDOW_LENGTH(3),
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (RAW_TYPE),
.DATA_WIDTH (16)
) Demosaic2_inst (
.clk (clk),
.reset (reset),
.in_data (Windows_data),
.out_data (Demosaic2_data),
.in_valid (Windows_valid),
.out_valid(Demosaic2_valid),
.in_ready (Blender_ready),
.out_ready(Demosaic2_ready),
.out_hsync(Demosaic2_hsync),
.out_fsync(Demosaic2_fsync)
);
ColorBlender #(
.IN_DEPTH(12), // 输入图像的色深
.OUT_DEPTH(COLOR_DEPTH) // 输出图像的色深
) ColorBlender_inst (
.clk (clk),
.reset (reset),
.in_data (Demosaic2_data),
.out_data (Blender_data),
.in_valid (Demosaic2_valid),
.out_valid(Blender_valid),
.in_ready (Crop_ready),
.out_ready(Blender_ready),
.in_hsync (Demosaic2_hsync),
.in_fsync (Demosaic2_fsync),
.out_hsync(Blender_hsync),
.out_fsync(Blender_fsync),
.gain_red (gain_red),
.gain_green(gain_green),
.gain_blue (gain_blue),
.enable (blender_enable)
);
Crop #(
.IN_WIDTH (IN_WIDTH),
.IN_HEIGHT (IN_HEIGHT),
.OFFSET_X (OFFSET_X),
.OFFSET_Y (OFFSET_Y),
.OUT_WIDTH (OUT_WIDTH),
.OUT_HEIGHT (OUT_HEIGHT),
.COLOR_DEPTH(COLOR_DEPTH)
) Crop_inst (
.clk (clk),
.reset (reset),
.in_data (Blender_data),
.out_data (Crop_data),
.in_valid (Blender_valid),
.out_valid(Crop_valid),
.in_ready (in_ready),
.out_ready(Crop_ready),
.in_hsync (Blender_hsync),
.in_fsync (Blender_fsync),
.out_hsync(Crop_hsync),
.out_fsync(Crop_fsync)
);
// reg [15:0] data_out_temp[8192];
// reg [31:0] now;
// reg [2:0] cnt_www;
// reg flag_ifdataerror;
// initial cnt_www = 0;
// always @(posedge reset) begin
// cnt_www <= cnt_www + 1;
// end
// integer i;
// always @(posedge clk) begin
// if(reset) begin
// flag_ifdataerror <= 0;
// if(cnt_www==1) for(i=0;i<8192;i=i+1) data_out_temp[i] <= 0;
// now <= 0;
// end else if(Crop_valid && in_ready)begin
// now <= now + 1;
// if(cnt_www==1)begin
// if(now<8192) data_out_temp[now] <= Crop_data[0];
// end else if(cnt_www==2)begin
// flag_ifdataerror <= (data_out_temp[now] != Crop_data[0]);
// end else flag_ifdataerror <= flag_ifdataerror;
// end
// end
endmodule
`timescale 1ns/1ps
module isp #(
parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088,
parameter reg [15:0] OUT_WIDTH = 1920,
parameter reg [15:0] OUT_HEIGHT = 1080,
parameter reg [ 4:0] COLOR_DEPTH = 8, // Can't Change!!!
parameter reg [ 1:0] RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
) (
// 基本信号
input wire clk,
input wire reset,
// 数据输入信号
input wire in_en,
input wire [15:0] in_data[3], // 数据输入线，0、1、2分别表示第一、二、三行
output wire out_ready, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
output wire out_receive,
// output wire out_clk,
output wire out_en,
output wire [3 * COLOR_DEPTH - 1:0] out_data,
input wire in_ready,
// input wire in_receive,
// 颜色校正，低八位为小数位，高八位为整数位
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire blender_enable, // 是否启用颜色校正
// Gamma矫正，低八位为小数位
// input wire [7:0] gamma_inverse,
input wire [7:0] gamma_table[256],
input wire gamma_enable,
// 白平衡
input wire [15:0] white_gain[3],
input wire [8:0] flame_rate,
input wire white_enable,
// 饱和度校正
input wire signed [31:0] saturation_inc,
input wire saturation_enable // -256~256
);
localparam reg [15:0] BAYER_WIDTH = IN_WIDTH - 2;
localparam reg [15:0] BAYER_HEIGHT = IN_HEIGHT - 2;
wire [COLOR_DEPTH - 1:0] w_out_data[3];
assign out_data = {w_out_data[2], w_out_data[1], w_out_data[0]};
// 颜色校正，并改变色深
wire blender_en, blender_ready, blender_receive;
wire [15:0] blender_r, blender_g, blender_b;
// 裁切图像
wire crop_en, crop_ready, crop_receive; // scaler 请求数据
reg [COLOR_DEPTH - 1:0] crop_data[3];
// Gamma矫正
wire gamma_en, gamma_ready, gamma_receive;
wire [COLOR_DEPTH - 1 : 0] gamma_data[3];
// 白平衡
wire white_en, white_ready, white_receive;
wire [COLOR_DEPTH - 1 : 0] white_data[3];
// 饱和度校正
wire saturation_en, saturation_ready, saturation_receive;
wire [COLOR_DEPTH - 1 : 0] saturation_data[3];
// reg in_receive;
// always @(posedge clk) in_receive <= in_en;
wire in_receive;
assign in_receive = out_en;
// assign out_clk = clk;
Demosaic2 #(
.IM_WIDTH (IN_WIDTH),
.IM_HEIGHT(IN_HEIGHT),
.RAW_TYPE (RAW_TYPE)
) inst_demosaic (
.clk(clk),
.reset(reset),
.in_en(in_en),
.in_data(in_data),
.out_ready(out_ready),
.out_receive(out_receive),
.out_en(blender_en),
.in_ready(blender_ready),
.in_receive(blender_receive),
.out_r(blender_r),
.out_g(blender_g),
.out_b(blender_b)
);
ColorBlender #(
.IN_DEPTH (12),
.OUT_DEPTH(COLOR_DEPTH)
) inst_blender (
.clk (clk),
.reset(reset),
.in_en(blender_en),
.in_data({blender_b, blender_g, blender_r}),
.out_ready(blender_ready),
.out_receive(blender_receive),
.in_ready(crop_ready),
.in_receive(crop_receive),
.out_en(crop_en),
.out_data(crop_data),
.gain_red(gain_red),
.gain_green(gain_green),
.gain_blue(gain_blue),
.enable(blender_enable)
);
Crop #(
.IN_WIDTH(BAYER_WIDTH),
.IN_HEIGHT(BAYER_HEIGHT),
.OUT_WIDTH(OUT_WIDTH),
.OUT_HEIGHT(OUT_HEIGHT),
.COLOR_DEPTH(COLOR_DEPTH)
) inst_crop (
.clk (clk),
.reset(reset),
.in_en(crop_en),
.out_ready(crop_ready),
.out_receive(crop_receive),
.in_data({crop_data[2], crop_data[1], crop_data[0]}),
.out_en(white_en),
.in_ready(white_ready),
.in_receive(white_receive),
.out_data({white_data[2], white_data[1], white_data[0]})
);
GreyWorld #(
.COLOR_DEPTH(COLOR_DEPTH),
.IM_SIZE({16'b0, OUT_WIDTH} * {16'b0, OUT_HEIGHT})
) inst_whitebalance (
.clk (clk),
.reset(reset),
.in_en(white_en),
.in_data(white_data),
.out_ready(white_ready),
.out_receive(white_receive),
.in_ready(gamma_ready),
.in_receive(gamma_receive),
.out_en(gamma_en),
.out_data(gamma_data),
.enable(white_enable),
.flame_rate(flame_rate),
.white_gain(white_gain)
);
// 查找表型Gamma校正
GammaCorrection #(
.COLOR_DEPTH(COLOR_DEPTH)
) inst_gamma (
.clk (clk),
.reset(reset),
.in_en(gamma_en),
.in_data(gamma_data),
.out_ready(gamma_ready),
.out_receive(gamma_receive),
.in_ready(saturation_ready),
.in_receive(saturation_receive),
.out_en(saturation_en),
.out_data(saturation_data),
.gamma_table(gamma_table),
.enable(gamma_enable)
);
SaturationCorrection #(
.COLOR_DEPTH(COLOR_DEPTH)
) inst_saturation (
.clk (clk),
.reset(reset),
.in_en(saturation_en),
.out_ready(saturation_ready),
.out_receive(saturation_receive),
.in_data(saturation_data),
.in_ready(in_ready),
.in_receive(in_receive),
.out_en(out_en),
.out_data(w_out_data),
.saturation_inc(saturation_inc),
.enable(saturation_enable)
);
endmodule

153
rtl/isp_Pipeline.sv Normal file
View File

@@ -0,0 +1,153 @@
`timescale 1ns / 1ps
module isp #(
parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088,
parameter OFFSET_X = 7,
parameter OFFSET_Y = 3,
parameter reg [15:0] OUT_WIDTH = 1920,
parameter reg [15:0] OUT_HEIGHT = 1080,
parameter reg [ 4:0] COLOR_DEPTH = 8, // Can't Change!!!
parameter reg [ 1:0] RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
) (
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [15:0] in_data[3], // 数据输入线，0、1、2分别表示第一、二、三行
output wire [3 * COLOR_DEPTH - 1:0] out_data,
// 数据有效信号
input wire in_valid,
output wire out_valid,
// 准备信号
input wire in_ready,
output wire out_ready,
// 颜色校正，低八位为小数位，高八位为整数位
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire blender_enable // 是否启用颜色校正
);
wire [15:0] Demosaic2_data[3];
wire [15:0] Windows_data[9];
wire [COLOR_DEPTH - 1 : 0] Blender_data[3];
wire [COLOR_DEPTH - 1 : 0] Crop_data[3];
wire Windows_valid, Demosaic2_valid, Blender_valid, Crop_valid;
wire Windows_ready, Demosaic2_ready, Blender_ready, Crop_ready;
wire Demosaic2_hsync, Blender_hsync, Crop_hsync;
wire Demosaic2_fsync, Blender_fsync, Crop_fsync;
assign out_valid = Crop_valid;
assign out_ready = Windows_ready;
assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]};
Windows #(
.DATA_WIDTH(16)
) Windows_inst (
.clk (clk),
.reset (reset),
.in_data (in_data),
.out_data (Windows_data),
.in_valid (in_valid),
.out_valid(Windows_valid),
.in_ready (Demosaic2_ready),
.out_ready(Windows_ready)
);
Demosaic #(
.WINDOW_LENGTH(3),
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (RAW_TYPE),
.DATA_WIDTH (16)
) Demosaic2_inst (
.clk (clk),
.reset (reset),
.in_data (Windows_data),
.out_data (Demosaic2_data),
.in_valid (Windows_valid),
.out_valid(Demosaic2_valid),
.in_ready (Blender_ready),
.out_ready(Demosaic2_ready),
.out_hsync(Demosaic2_hsync),
.out_fsync(Demosaic2_fsync)
);
ColorBlender #(
.IN_DEPTH(12), // 输入图像的色深
.OUT_DEPTH(COLOR_DEPTH) // 输出图像的色深
) ColorBlender_inst (
.clk (clk),
.reset (reset),
.in_data (Demosaic2_data),
.out_data (Blender_data),
.in_valid (Demosaic2_valid),
.out_valid(Blender_valid),
.in_ready (Crop_ready),
.out_ready(Blender_ready),
.in_hsync (Demosaic2_hsync),
.in_fsync (Demosaic2_fsync),
.out_hsync(Blender_hsync),
.out_fsync(Blender_fsync),
.gain_red (gain_red),
.gain_green(gain_green),
.gain_blue (gain_blue),
.enable (blender_enable)
);
Crop #(
.IN_WIDTH (IN_WIDTH),
.IN_HEIGHT (IN_HEIGHT),
.OFFSET_X (OFFSET_X),
.OFFSET_Y (OFFSET_Y),
.OUT_WIDTH (OUT_WIDTH),
.OUT_HEIGHT (OUT_HEIGHT),
.COLOR_DEPTH(COLOR_DEPTH)
) Crop_inst (
.clk (clk),
.reset (reset),
.in_data (Blender_data),
.out_data (Crop_data),
.in_valid (Blender_valid),
.out_valid(Crop_valid),
.in_ready (in_ready),
.out_ready(Crop_ready),
.in_hsync (Blender_hsync),
.in_fsync (Blender_fsync),
.out_hsync(Crop_hsync),
.out_fsync(Crop_fsync)
);
// reg [15:0] data_out_temp[8192];
// reg [31:0] now;
// reg [2:0] cnt_www;
// reg flag_ifdataerror;
// initial cnt_www = 0;
// always @(posedge reset) begin
// cnt_www <= cnt_www + 1;
// end
// integer i;
// always @(posedge clk) begin
// if(reset) begin
// flag_ifdataerror <= 0;
// if(cnt_www==1) for(i=0;i<8192;i=i+1) data_out_temp[i] <= 0;
// now <= 0;
// end else if(Crop_valid && in_ready)begin
// now <= now + 1;
// if(cnt_www==1)begin
// if(now<8192) data_out_temp[now] <= Crop_data[0];
// end else if(cnt_www==2)begin
// flag_ifdataerror <= (data_out_temp[now] != Crop_data[0]);
// end else flag_ifdataerror <= flag_ifdataerror;
// end
// end
endmodule

0
rtl/isp_tb.sv → rtl/isp_Pipeline_tb.sv
View File