113 lines
3.9 KiB
Systemverilog
113 lines
3.9 KiB
Systemverilog
`timescale 1ns / 1ps
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module Demosaic #(
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parameter WINDOW_LENGTH = 3,
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parameter reg [15:0] TOTAL_WIDTH = 512+3, // 总图像宽度
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parameter reg [15:0] TOTAL_HEIGHT = 256+3, // 总图像高度
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parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
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parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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)(
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input wire clk,
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input wire reset,
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input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
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output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready,
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output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
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output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
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);
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localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
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localparam PIPILINE = 3;
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reg [PIPILINE-1:0] pipeline_valid;
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wire pipeline_running;
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assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_running;
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = pipeline_valid[PIPILINE-1];
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reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
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reg [31:0] pos_x, pos_y, temp_pos_x, temp_pos_y;
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reg [DATA_WIDTH-1:0] red, blue, green;
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reg [1:0] raw_type;
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0;
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pipeline_valid <= 0;
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{red, green, blue} <= 0;
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{out_data[2],out_data[1],out_data[0]} <= 0;
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{out_hsync,out_fsync} <= 0;
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pos_x <= ~0;
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pos_y <= ~0;
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temp_pos_x <= 0;
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temp_pos_y <= 0;
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end else if(pipeline_running) begin
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pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
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if(in_valid) begin
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for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= in_data[i];
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pos_x <= (pos_x >= TOTAL_WIDTH - 1)?(0):(pos_x + 1);
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pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
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end
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if(pipeline_valid[0]) begin
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temp_pos_x <= pos_x;
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temp_pos_y <= pos_y;
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case (raw_type)
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0: begin // Missing B, R on G
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blue <= (data_cache[1] + data_cache[7]) >> 1;
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red <= (data_cache[3] + data_cache[5]) >> 1;
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green <= data_cache[4];
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end
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1: begin // Missing G, R on B
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green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
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red <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
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blue <= data_cache[4];
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end
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2: begin // Missing G, B on R
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green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
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blue <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
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red <= data_cache[4];
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end
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3: begin // Missing B, R on G
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red <= (data_cache[1] + data_cache[7]) >> 1;
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blue <= (data_cache[3] + data_cache[5]) >> 1;
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green <= data_cache[4];
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end
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endcase
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end
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if(pipeline_valid[1]) begin
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{out_data[2],out_data[1],out_data[0]} <= {red,blue,green};
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out_hsync <= (temp_pos_x == 0);
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out_fsync <= ((temp_pos_x == 0) && (temp_pos_y == 0));
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end
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end
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end
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// 0:gr 1:rg 2:bg 3:gb 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
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// bg gb gr rg
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always @(*) begin
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if(reset) raw_type = RAW_TYPE;
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else case (RAW_TYPE)
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2'b00: raw_type = {pos_y[0], pos_x[0]};
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2'b01: raw_type = {pos_y[0], ~pos_x[0]};
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2'b10: raw_type = {~pos_y[0], pos_x[0]};
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2'b11: raw_type = {~pos_y[0], ~pos_x[0]};
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endcase
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end
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endmodule
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