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add pipeline and pass sim

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SikongJueluo
2024-10-22 20:31:51 +08:00
parent f4efa6177e
commit 1ab1467569
18 changed files with 848 additions and 957 deletions
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27
rtl/Color/ColorBlender_Pipeline.sv
View File

@@ -2,24 +2,24 @@
// 三通道图像合成一个RGB图像
module ColorBlender_Pipeline #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] DATA_WIDTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
input wire [DATA_WIDTH - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
@@ -29,7 +29,6 @@ module ColorBlender_Pipeline #(
input wire [15:0] gain_blue,
input wire enable
);
localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
@@ -65,9 +64,9 @@ module ColorBlender_Pipeline #(
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[0] <= (in_data[0]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[1] <= (in_data[1]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[2] <= (in_data[2]) << (8 - (DATA_WIDTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
@@ -83,9 +82,9 @@ module ColorBlender_Pipeline #(
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
data_cal2[0] <= (|data_cal1[0][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (|data_cal1[1][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (|data_cal1[2][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin

85
rtl/Color/GammaCorrection_Pipeline.sv Executable file
View File

@@ -0,0 +1,85 @@
`timescale 1ns / 1ps
module GammaCorrection_Pipeline #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_valid,
output reg out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
output wire out_hsync,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
input wire [7:0] gamma_table[256],
input wire enable
);
reg [7:0] data_cache[3];
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk)
begin
if (reset)
begin
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
end
else
begin
case (state)
READ_DATA:
begin
if (in_en)
begin
data_cache[0] <= in_data[0];
data_cache[1] <= in_data[1];
data_cache[2] <= in_data[2];
end
end
SEND_DATA:
begin
if (in_ready && !in_receive)
begin
out_en <= 1;
if (enable)
begin
out_data[0] <= gamma_table[data_cache[0]];
out_data[1] <= gamma_table[data_cache[1]];
out_data[2] <= gamma_table[data_cache[2]];
end
else
begin
out_data[0] <= data_cache[0];
out_data[1] <= data_cache[1];
out_data[2] <= data_cache[2];
end
end
else
out_en <= 0;
end
default:
;
endcase
end
end
endmodule