add pipeline and pass sim
This commit is contained in:
298
rtl/BayerProcess/DPC.sv
Normal file
298
rtl/BayerProcess/DPC.sv
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@@ -0,0 +1,298 @@
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`timescale 1ns / 1ps
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module DPC #(
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parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
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parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
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parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
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parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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) (
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input wire clk,
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input wire reset,
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input wire [DATA_WIDTH - 1:0] in_data [5*5],
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output reg [DATA_WIDTH - 1:0] out_data,
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready
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);
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localparam WINDOW_LENGTH = 5;
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localparam DATA_NUM = WINDOW_LENGTH * WINDOW_LENGTH;
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localparam EXPAND_BITS = 5;
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localparam PIPILINE = 9;
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reg [PIPILINE-1:0] pipeline_valid;
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wire pipeline_running;
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assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_running;
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = pipeline_valid[PIPILINE-1];
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reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
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reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
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reg [DATA_WIDTH-1:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点
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reg [DATA_WIDTH-1:0]
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channel_cache0,
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channel_cache1,
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channel_cache2,
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channel_cache3,
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channel_cache4; // 缓存中心像素点的颜色数据
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0]
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grad_h_cache[3], grad_v_cache[3], grad_45_cache[3], grad_135_cache[3];
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reg [DATA_WIDTH-1+EXPAND_BITS:0]
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grad_h_cache0[3], grad_v_cache0[3], grad_45_cache0[3], grad_135_cache0[3];
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reg [DATA_WIDTH-1+EXPAND_BITS:0]
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grad_h_cache1[3], grad_v_cache1[3], grad_45_cache1[3], grad_135_cache1[3];
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reg [DATA_WIDTH-1+EXPAND_BITS:0]
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grad_h_cache2[3], grad_v_cache2[3], grad_45_cache2[3], grad_135_cache2[3];
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reg [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
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reg [1:0] flag_which_dict;
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reg [DATA_WIDTH-1:0]
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channel_cache_correct[4],
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channel_cache_correct0[4],
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channel_cache_correct1[4],
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channel_cache_correct2[4];
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reg [DATA_WIDTH-1:0] channel_cache_correct_final;
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reg flag_if_need_corection;
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reg [15:0] pos_x;
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reg pos_y_bit;
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reg [1:0] raw_type;
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0;
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for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0;
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for (i = 0; i < 9; i = i + 1) channel_cache[i] <= 0;
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channel_cache0 <= 0;
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channel_cache1 <= 0;
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channel_cache2 <= 0;
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channel_cache3 <= 0;
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channel_cache4 <= 0;
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channel_cache_correct_final <= 0;
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for (i = 0; i < 3; i = i + 1) grad_h_cache[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_h_cache1[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_h_cache2[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_v_cache[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_v_cache1[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_v_cache2[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_45_cache[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_45_cache1[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_45_cache2[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_135_cache[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_135_cache1[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_135_cache2[i] <= 0;
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for (i = 0; i < 3; i = i + 1) grad_median_cache[i] <= 0;
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flag_which_dict <= 0;
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flag_if_need_corection <= 0;
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for (i = 0; i < 4; i = i + 1) channel_cache_correct[i] <= 0;
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for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= 0;
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for (i = 0; i < 4; i = i + 1) channel_cache_correct0[i] <= 0;
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for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= 0;
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pipeline_valid <= 0;
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out_data <= 0;
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pos_x <= ~0;
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pos_y_bit <= ~0;
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raw_type <= RAW_TYPE;
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end else if (pipeline_running) begin
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pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
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if (in_valid) begin
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for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i];
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pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1);
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pos_y_bit <= (pos_x >= TOTAL_WIDTH - 1) ? (~pos_y_bit) : (pos_y_bit);
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end
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if (pipeline_valid[0]) begin
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for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i];
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case (RAW_TYPE)
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2'b00: raw_type <= {pos_y_bit, pos_x[0]};
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2'b01: raw_type <= {pos_y_bit, ~pos_x[0]};
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2'b10: raw_type <= {~pos_y_bit, pos_x[0]};
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2'b11: raw_type <= {~pos_y_bit, ~pos_x[0]};
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endcase
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end
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if (pipeline_valid[1]) begin
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case (raw_type)
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1, 2: begin
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channel_cache[0] <= data_cache[00];
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channel_cache[1] <= data_cache[10];
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channel_cache[2] <= data_cache[20];
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channel_cache[3] <= data_cache[02];
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channel_cache[4] <= data_cache[12];
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channel_cache[5] <= data_cache[22];
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channel_cache[6] <= data_cache[04];
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channel_cache[7] <= data_cache[14];
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channel_cache[8] <= data_cache[24];
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end
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0, 3: begin
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channel_cache[0] <= data_cache[02];
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channel_cache[1] <= data_cache[06];
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channel_cache[2] <= data_cache[10];
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channel_cache[3] <= data_cache[08];
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channel_cache[4] <= data_cache[12];
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channel_cache[5] <= data_cache[16];
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channel_cache[6] <= data_cache[14];
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channel_cache[7] <= data_cache[18];
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channel_cache[8] <= data_cache[22];
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end
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endcase
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end
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if (pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算
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channel_cache0 <= channel_cache[4];
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grad_h_cache[0] <= channel_cache[0] + channel_cache[2] - 2 * channel_cache[1];
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grad_h_cache[1] <= channel_cache[3] + channel_cache[5] - 2 * channel_cache[4];
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grad_h_cache[2] <= channel_cache[6] + channel_cache[8] - 2 * channel_cache[7];
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grad_v_cache[0] <= channel_cache[0] + channel_cache[6] - 2 * channel_cache[3];
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grad_v_cache[1] <= channel_cache[1] + channel_cache[7] - 2 * channel_cache[4];
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grad_v_cache[2] <= channel_cache[2] + channel_cache[8] - 2 * channel_cache[5];
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grad_45_cache[0] <= 2 * (channel_cache[1] - channel_cache[3]);
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grad_45_cache[1] <= channel_cache[6] + channel_cache[2] - 2 * channel_cache[4];
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grad_45_cache[2] <= 2 * (channel_cache[7] - channel_cache[5]);
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grad_135_cache[0] <= 2 * (channel_cache[1] - channel_cache[5]);
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grad_135_cache[1] <= channel_cache[0] + channel_cache[8] - 2 * channel_cache[4];
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grad_135_cache[2] <= 2 * (channel_cache[3] - channel_cache[7]);
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channel_cache_correct[0] <= channel_cache[3] / 2 + channel_cache[5] / 2;
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channel_cache_correct[1] <= channel_cache[1] / 2 + channel_cache[7] / 2;
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channel_cache_correct[2] <= channel_cache[2] / 2 + channel_cache[6] / 2;
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channel_cache_correct[3] <= channel_cache[0] / 2 + channel_cache[8] / 2;
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end
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if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算,注意grad_h_cache等是singed，可能为负数
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channel_cache1 <= channel_cache0;
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grad_h_cache0 [0] <= grad_h_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [0] + 1) : (grad_h_cache [0]);
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grad_h_cache0 [1] <= grad_h_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [1] + 1) : (grad_h_cache [1]);
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grad_h_cache0 [2] <= grad_h_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [2] + 1) : (grad_h_cache [2]);
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grad_v_cache0 [0] <= grad_v_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [0] + 1) : (grad_v_cache [0]);
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grad_v_cache0 [1] <= grad_v_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [1] + 1) : (grad_v_cache [1]);
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grad_v_cache0 [2] <= grad_v_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [2] + 1) : (grad_v_cache [2]);
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grad_45_cache0 [0] <= grad_45_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [0] + 1) : (grad_45_cache [0]);
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grad_45_cache0 [1] <= grad_45_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [1] + 1) : (grad_45_cache [1]);
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grad_45_cache0 [2] <= grad_45_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [2] + 1) : (grad_45_cache [2]);
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grad_135_cache0[0] <= grad_135_cache[0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[0] + 1) : (grad_135_cache[0]);
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grad_135_cache0[1] <= grad_135_cache[1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[1] + 1) : (grad_135_cache[1]);
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grad_135_cache0[2] <= grad_135_cache[2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[2] + 1) : (grad_135_cache[2]);
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channel_cache_correct0[0] <= channel_cache_correct[0] + grad_h_cache[0]/4 + grad_h_cache[2]/4;
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channel_cache_correct0[1] <= channel_cache_correct[1] + grad_v_cache[0]/4 + grad_v_cache[2]/4;
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channel_cache_correct0[2] <= channel_cache_correct[2] + grad_45_cache[0]/4 + grad_45_cache[2]/4;
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channel_cache_correct0[3] <= channel_cache_correct[3] + grad_135_cache[0]/4 + grad_135_cache[2]/4;
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end
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if (pipeline_valid[4]) begin //计算中位数
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channel_cache2 <= channel_cache1;
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for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= channel_cache_correct0[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache1[i] <= grad_h_cache0[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache1[i] <= grad_v_cache0[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache1[i] <= grad_45_cache0[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache1[i] <= grad_135_cache0[i];
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grad_median_cache[0] <= MEDIAN(grad_h_cache0);
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grad_median_cache[1] <= MEDIAN(grad_v_cache0);
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grad_median_cache[2] <= MEDIAN(grad_45_cache0);
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grad_median_cache[3] <= MEDIAN(grad_135_cache0);
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end
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if (pipeline_valid[5]) begin //计算最小值，判断最小梯度方向
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channel_cache3 <= channel_cache2;
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for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= channel_cache_correct1[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache2[i] <= grad_h_cache1[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache2[i] <= grad_v_cache1[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache2[i] <= grad_45_cache1[i];
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for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache2[i] <= grad_135_cache1[i];
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flag_which_dict <= MIN(grad_median_cache);
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end
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if (pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点
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channel_cache4 <= channel_cache3;
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channel_cache_correct_final <= channel_cache_correct2[flag_which_dict];
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case (flag_which_dict)
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2'b00:
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flag_if_need_corection <= grad_h_cache2[1] > 4 * (grad_h_cache2[0] + grad_h_cache2[2]);
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2'b01:
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flag_if_need_corection <= grad_v_cache2[1] > 4 * (grad_v_cache2[0] + grad_v_cache2[2]);
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2'b10:
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flag_if_need_corection <= grad_45_cache2[1] > 3 * (grad_45_cache2[0] + grad_45_cache2[2]);
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2'b11:
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flag_if_need_corection <= grad_135_cache2[1] > 3*(grad_135_cache2[0] + grad_135_cache2[2]);
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endcase
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end
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if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值
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out_data <= (flag_if_need_corection) ? (channel_cache_correct_final) : (channel_cache4);
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end
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end
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end
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function [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN;
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input [DATA_WIDTH-1+EXPAND_BITS:0] inx[3];
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begin
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if ((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0]))
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MEDIAN = inx[1];
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else if ((inx[1] >= inx[0]) || (inx[0] >= inx[1])) MEDIAN = inx[0];
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else MEDIAN = inx[2];
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end
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endfunction
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function [1:0] MIN;
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input [DATA_WIDTH-1+EXPAND_BITS:0] inx[4];
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begin
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if (inx[0] >= inx[1] && inx[0] >= inx[2] && inx[0] >= inx[3]) MIN = 2'b00;
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else if (inx[1] >= inx[0] && inx[1] >= inx[2] && inx[1] >= inx[3]) MIN = 2'b01;
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else if (inx[2] >= inx[0] && inx[2] >= inx[1] && inx[2] >= inx[3]) MIN = 2'b10;
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else MIN = 2'b11;
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end
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endfunction
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/*
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00 05 10 15 20
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01 06 11 16 21 0 1 2
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02 07 12 17 22 -> 3 4 5
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03 08 13 18 23 6 7 8
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04 09 14 19 24
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rawtype==0: center is GREEN
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g r g r g / / g / /
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b g b g b / g / g /
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g r g r g -> g / G / g
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b g b g b / g / g /
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g r g r g / / g / /
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rawtype==1: center is RED
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r g r g r r / r / r
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g b g b g / / / / /
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r g r g r -> r / R / r
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g b g b g / / / / /
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r g r g r r / r / r
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rawtype==2: center is BLUE
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b g b g b b / b / b
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g r g r g / / / / /
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b g b g b -> b / B / b
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g r g r g / / / / /
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b g b g b b / b / b
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rawtype==3: center is GREEN
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g b g b g / / g / /
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r g r g r / g / g /
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g b g b g -> g / G / g
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r g r g r / g / g /
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r g r g r / / g / /
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*/
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endmodule
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230
rtl/BayerProcess/Demosaic2.sv
Normal file
230
rtl/BayerProcess/Demosaic2.sv
Normal file
@@ -0,0 +1,230 @@
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`timescale 1ns/1ps
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module Demosaic2 #(
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parameter reg [15:0] IM_WIDTH = 512, // 图像宽度
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parameter reg [15:0] IM_HEIGHT = 256, // 图像高度
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parameter reg [ 1:0] RAW_TYPE = 3, // 0:grbg 1:rggb 2:bggr 3:gbrg
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parameter reg [ 4:0] DATA_SIZE = 16
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) (
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// 基本信号
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input wire clk,
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input wire reset,
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// 数据输入信号
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input wire in_en,
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input wire [DATA_SIZE - 1:0] in_data [3], // 数据输入线，0、1、2分别表示第一、二、三行
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output wire out_ready, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
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output wire out_receive,
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// en: 输出数据有效信号，高电平有效
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input wire in_ready,
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input wire in_receive,
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output reg out_en,
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output reg [DATA_SIZE - 1:0] out_r,
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output reg [DATA_SIZE - 1:0] out_g,
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output reg [DATA_SIZE - 1:0] out_b
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);
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// 常量，包括状态机
|
||||
// localparam IM_SIZE = IM_HEIGHT * IM_WIDTH;
|
||||
localparam reg [2:0] READ_DATA = 0;
|
||||
localparam reg [2:0] COLOR_GEN = 1;
|
||||
localparam reg [2:0] SEND_DATA = 2;
|
||||
localparam reg [2:0] SLIDE_WINDOW = 3;
|
||||
|
||||
// 寄存器
|
||||
reg [2:0] state, nextState;
|
||||
reg [15:0] data_cache[9]; // 缓存颜色数据，行列3x3
|
||||
reg [15:0] pos_x, pos_y; // 滑动窗口左上角位置
|
||||
reg [2:0] cnt_data; // 记录输入数据数量，最大值256
|
||||
reg [1:0] raw_type;
|
||||
reg [15:0] red, blue, green;
|
||||
|
||||
// 三段状态机实现，窗口滑动，颜色计算
|
||||
// 状态切换
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (reset)
|
||||
state <= READ_DATA;
|
||||
else
|
||||
state <= nextState;
|
||||
end
|
||||
|
||||
// 下一状态更新
|
||||
always @(*)
|
||||
begin
|
||||
case (state)
|
||||
// 记录够3x3个数据后，进行rgb转换
|
||||
READ_DATA:
|
||||
nextState = (cnt_data >= 3) ? COLOR_GEN : READ_DATA;
|
||||
COLOR_GEN:
|
||||
nextState = SEND_DATA;
|
||||
SEND_DATA:
|
||||
nextState = (in_receive) ? SLIDE_WINDOW : SEND_DATA;
|
||||
SLIDE_WINDOW:
|
||||
nextState = READ_DATA;
|
||||
default:
|
||||
nextState = READ_DATA;
|
||||
endcase
|
||||
end
|
||||
|
||||
// 请求数据
|
||||
assign out_ready = (cnt_data <= 2 && !in_en && state == READ_DATA && !reset) ? 1 : 0;
|
||||
// 收到数据
|
||||
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
|
||||
|
||||
// 各状态执行的操作
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
// 外部输出初始化
|
||||
out_en <= 0;
|
||||
out_r <= 0;
|
||||
out_g <= 0;
|
||||
out_r <= 0;
|
||||
|
||||
// 内部寄存器初始化
|
||||
pos_x <= 0;
|
||||
pos_y <= 0;
|
||||
cnt_data <= 0;
|
||||
raw_type <= RAW_TYPE;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// 状态机执行
|
||||
case (state)
|
||||
// 读取数据
|
||||
READ_DATA:
|
||||
begin
|
||||
if (in_en)
|
||||
begin
|
||||
data_cache[0 + cnt_data * 3] <= in_data[0];
|
||||
data_cache[1 + cnt_data * 3] <= in_data[1];
|
||||
data_cache[2 + cnt_data * 3] <= in_data[2];
|
||||
|
||||
cnt_data <= cnt_data + 1;
|
||||
end
|
||||
end
|
||||
|
||||
COLOR_GEN:
|
||||
begin
|
||||
// 生成rgb图像
|
||||
// data case 0 case 1 case 2 case 3
|
||||
// 0 3 6 G R G R G R B G B G B G
|
||||
// 1 4 7 B G B G B G G R G R G R
|
||||
// 2 5 8 G R G R G R B G B G B G
|
||||
case (raw_type)
|
||||
0:
|
||||
begin // Missing B, R on G
|
||||
blue <= (data_cache[1] + data_cache[7]) >> 1;
|
||||
red <= (data_cache[3] + data_cache[5]) >> 1;
|
||||
green <= data_cache[4];
|
||||
end
|
||||
|
||||
1:
|
||||
begin // Missing G, R on B
|
||||
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
|
||||
red <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
|
||||
blue <= data_cache[4];
|
||||
end
|
||||
|
||||
2:
|
||||
begin // Missing G, B on R
|
||||
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
|
||||
blue <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
|
||||
red <= data_cache[4];
|
||||
end
|
||||
|
||||
|
||||
3:
|
||||
begin // Missing B, R on G
|
||||
red <= (data_cache[1] + data_cache[7]) >> 1;
|
||||
blue <= (data_cache[3] + data_cache[5]) >> 1;
|
||||
green <= data_cache[4];
|
||||
end
|
||||
default:
|
||||
;
|
||||
endcase
|
||||
|
||||
case (raw_type)
|
||||
0:
|
||||
raw_type <= 1;
|
||||
1:
|
||||
raw_type <= 0;
|
||||
2:
|
||||
raw_type <= 3;
|
||||
3:
|
||||
raw_type <= 2;
|
||||
endcase
|
||||
end
|
||||
|
||||
SEND_DATA:
|
||||
begin
|
||||
if (in_ready && !in_receive)
|
||||
begin
|
||||
out_en <= 1;
|
||||
out_r <= red;
|
||||
out_b <= blue;
|
||||
out_g <= green;
|
||||
pos_x <= pos_x + 1;
|
||||
end
|
||||
else
|
||||
out_en <= 0;
|
||||
end
|
||||
|
||||
SLIDE_WINDOW:
|
||||
begin
|
||||
// 记录位置寄存器自增，并处理缓存数据
|
||||
if (pos_x >= IM_WIDTH - 2)
|
||||
begin
|
||||
cnt_data <= 0;
|
||||
pos_x <= 0;
|
||||
pos_y <= pos_y + 1;
|
||||
if (pos_y >= IM_HEIGHT - 2)
|
||||
begin
|
||||
pos_y <= 0;
|
||||
end
|
||||
// 换行后切换Bayer格式
|
||||
if (pos_y % 2 == 1)
|
||||
begin
|
||||
raw_type <= RAW_TYPE;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case (RAW_TYPE)
|
||||
0:
|
||||
raw_type <= 2;
|
||||
1:
|
||||
raw_type <= 3;
|
||||
2:
|
||||
raw_type <= 0;
|
||||
3:
|
||||
raw_type <= 1;
|
||||
default:
|
||||
;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt_data <= 2;
|
||||
|
||||
// 窗口右移
|
||||
data_cache[0] <= data_cache[3];
|
||||
data_cache[1] <= data_cache[4];
|
||||
data_cache[2] <= data_cache[5];
|
||||
data_cache[3] <= data_cache[6];
|
||||
data_cache[4] <= data_cache[7];
|
||||
data_cache[5] <= data_cache[8];
|
||||
end
|
||||
end
|
||||
|
||||
default:
|
||||
;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
121
rtl/BayerProcess/Demosaic_Pipeline.sv
Normal file
121
rtl/BayerProcess/Demosaic_Pipeline.sv
Normal file
@@ -0,0 +1,121 @@
|
||||
`timescale 1ns / 1ps
|
||||
module Demosaic_Pipeline #(
|
||||
parameter WINDOW_LENGTH = 3,
|
||||
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
|
||||
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
|
||||
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
|
||||
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
|
||||
output reg [DATA_WIDTH - 1:0] out_data[3], // 数据输出线，3、2、1分别表示r、g、b
|
||||
|
||||
input wire in_valid,
|
||||
output wire out_valid,
|
||||
|
||||
input wire in_ready,
|
||||
output wire out_ready,
|
||||
|
||||
output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
|
||||
output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
|
||||
);
|
||||
|
||||
localparam DATA_NUM = WINDOW_LENGTH * WINDOW_LENGTH;
|
||||
localparam PIPILINE = 4;
|
||||
|
||||
reg [PIPILINE-1:0] pipeline_valid;
|
||||
wire pipeline_running;
|
||||
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
|
||||
|
||||
//out_ready ：只要本模块可以接收数据就一直拉高
|
||||
assign out_ready = pipeline_running;
|
||||
//out_valid ：只要本模块可以发出数据就一直拉高
|
||||
assign out_valid = pipeline_valid[PIPILINE-1];
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_cache [DATA_NUM]; // 缓存颜色数据，行列nxn
|
||||
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
|
||||
reg [31:0] pos_x, pos_y, temp_pos_x1, temp_pos_y1, temp_pos_x2, temp_pos_y2;
|
||||
reg [DATA_WIDTH-1:0] red, blue, green;
|
||||
reg [1:0] raw_type;
|
||||
|
||||
integer i;
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0;
|
||||
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0;
|
||||
pipeline_valid <= 0;
|
||||
{red, green, blue} <= 0;
|
||||
{out_data[2], out_data[1], out_data[0]} <= 0;
|
||||
{out_hsync, out_fsync} <= 0;
|
||||
pos_x <= ~0;
|
||||
pos_y <= ~0;
|
||||
temp_pos_x1 <= ~0;
|
||||
temp_pos_y1 <= ~0;
|
||||
temp_pos_x2 <= ~0;
|
||||
temp_pos_y2 <= ~0;
|
||||
raw_type <= RAW_TYPE;
|
||||
end else if (pipeline_running) begin
|
||||
|
||||
// First level pipeline for reading data
|
||||
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
|
||||
|
||||
if (in_valid) begin
|
||||
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i];
|
||||
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1);
|
||||
pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
|
||||
end
|
||||
|
||||
if (pipeline_valid[0]) begin
|
||||
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i];
|
||||
temp_pos_x1 <= pos_x;
|
||||
temp_pos_y1 <= pos_y;
|
||||
case (RAW_TYPE)
|
||||
2'b00: raw_type <= {pos_y[0], pos_x[0]};
|
||||
2'b01: raw_type <= {pos_y[0], ~pos_x[0]};
|
||||
2'b10: raw_type <= {~pos_y[0], pos_x[0]};
|
||||
2'b11: raw_type <= {~pos_y[0], ~pos_x[0]};
|
||||
endcase
|
||||
end
|
||||
|
||||
if (pipeline_valid[1]) begin
|
||||
temp_pos_x2 <= temp_pos_x1;
|
||||
temp_pos_y2 <= temp_pos_y1;
|
||||
case (raw_type)
|
||||
0: begin // Missing B, R on G
|
||||
blue <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
|
||||
red <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
|
||||
green <= data_cache[4];
|
||||
end
|
||||
1: begin // Missing G, R on B
|
||||
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
|
||||
red <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
|
||||
blue <= data_cache[4];
|
||||
end
|
||||
2: begin // Missing G, B on R
|
||||
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
|
||||
blue <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
|
||||
red <= data_cache[4];
|
||||
end
|
||||
3: begin // Missing B, R on G
|
||||
red <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
|
||||
blue <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
|
||||
green <= data_cache[4];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
if (pipeline_valid[2]) begin
|
||||
{out_data[2], out_data[1], out_data[0]} <= {red, blue, green};
|
||||
out_hsync <= (temp_pos_x2 == 0);
|
||||
out_fsync <= ((temp_pos_x2 == 0) && (temp_pos_y2 == 0));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 0:grg 1:rgr 2:bgb 3:gbg 036 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
|
||||
// bgb gbg grg rgr 147
|
||||
// grg rgr bgb gbg 258
|
||||
endmodule
|
||||
|
||||
35
rtl/BayerProcess/Gowin_SDPB.sv
Normal file
35
rtl/BayerProcess/Gowin_SDPB.sv
Normal file
@@ -0,0 +1,35 @@
|
||||
//Gowin SDPB IP<49>˷<EFBFBD><CBB7><EFBFBD><EFBFBD>ļ<EFBFBD>
|
||||
`timescale 1ns / 1ps
|
||||
module Gowin_SDPB (
|
||||
input wire clka,
|
||||
input wire clkb, //no use
|
||||
input wire reset,
|
||||
|
||||
input wire cea,
|
||||
input wire ceb,
|
||||
|
||||
input wire [10:0] ada,
|
||||
input wire [10:0] adb,
|
||||
|
||||
input wire [15:0] din,
|
||||
output reg [15:0] dout,
|
||||
|
||||
input wire oce //no use
|
||||
);
|
||||
|
||||
reg [15:0] bram[2048];
|
||||
integer i;
|
||||
initial for (i = 0; i < 2048; i = i + 1) bram[i] = 0;
|
||||
|
||||
always @(posedge clka) begin
|
||||
if (reset) for (i = 0; i < 2048; i = i + 1) bram[i] <= 0;
|
||||
else if (cea) bram[ada] <= din;
|
||||
end
|
||||
|
||||
always @(posedge clka) begin
|
||||
if (reset) dout <= 0;
|
||||
else if (ceb) dout <= bram[adb];
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
72
rtl/BayerProcess/SHIFT_REGISTER.sv
Normal file
72
rtl/BayerProcess/SHIFT_REGISTER.sv
Normal file
@@ -0,0 +1,72 @@
|
||||
//RAM-BASED移位寄存器
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module SHIFT_REGISTER #(
|
||||
parameter reg [4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
|
||||
parameter IMAGE_WIDTH = 1936, //MAX 2048
|
||||
parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满
|
||||
) (
|
||||
// 基本信号
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
// 数据线
|
||||
input wire [DATA_WIDTH - 1:0] in_data,
|
||||
output wire [DATA_WIDTH - 1:0] out_data,
|
||||
// 有效信号
|
||||
input wire in_valid, // 上一模块输出数据有效
|
||||
output wire out_valid // 当前模块输出数据有效
|
||||
);
|
||||
|
||||
reg [10:0] addr_a, addr_b;
|
||||
wire cea, ceb;
|
||||
reg fulldone;
|
||||
|
||||
reg in_valid_temp0, in_valid_temp1;
|
||||
always @(posedge clk) in_valid_temp0 <= in_valid && (fulldone || IFOUTIMME);
|
||||
always @(posedge clk) in_valid_temp1 <= in_valid_temp0;
|
||||
|
||||
assign cea = in_valid;
|
||||
assign ceb = in_valid_temp0;
|
||||
assign out_valid = in_valid_temp1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) fulldone <= 0;
|
||||
else if (addr_b == IMAGE_WIDTH - 1) fulldone <= 1;
|
||||
else fulldone <= fulldone;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
addr_a <= IMAGE_WIDTH + 1;
|
||||
addr_b <= 0;
|
||||
end else if (cea) begin
|
||||
addr_a <= addr_a + 1;
|
||||
addr_b <= addr_b + 1;
|
||||
end else begin
|
||||
addr_a <= addr_a;
|
||||
addr_b <= addr_b;
|
||||
end
|
||||
end
|
||||
|
||||
// Single-Double-Port-BRAM-IP Bypass Normal
|
||||
Gowin_SDPB Gowin_SDPB_inst (
|
||||
.clka (clk), //input clka
|
||||
.clkb (clk), //input clkb
|
||||
.reset(reset), //input reset
|
||||
|
||||
.cea(cea), //input cea
|
||||
.ceb(ceb), //input ceb
|
||||
|
||||
.ada(addr_a), //input [10:0] ada
|
||||
.adb(addr_b), //input [10:0] adb
|
||||
|
||||
.din (in_data), //input [15:0] din
|
||||
.dout(out_data), //output [15:0] dout
|
||||
|
||||
.oce(1) //input oce
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
119
rtl/BayerProcess/Windows.sv
Normal file
119
rtl/BayerProcess/Windows.sv
Normal file
@@ -0,0 +1,119 @@
|
||||
`timescale 1ns / 1ps
|
||||
module Windows #(
|
||||
parameter DATA_WIDTH = 16,
|
||||
parameter IMAGE_WIDTH = 1936,
|
||||
parameter IMAGE_HEIGHT = 1088,
|
||||
parameter WINDOWS_WIDTH = 3,
|
||||
parameter WINDOWS_ANCHOR_X = 1, //禁止大于WINDOWS_WIDTH-1
|
||||
parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1
|
||||
) (
|
||||
// 基本信号
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
// 数据线
|
||||
input wire [DATA_WIDTH - 1:0] in_data,
|
||||
output reg [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线
|
||||
// 有效信号
|
||||
input wire in_valid, // 上一模块输出数据有效
|
||||
output reg out_valid, // 当前模块输出数据有效
|
||||
// 准备信号 Windows模块无法停止，因此默认不处理准备信号
|
||||
input wire in_ready,
|
||||
output wire out_ready
|
||||
);
|
||||
|
||||
assign out_ready = 1'b1;
|
||||
|
||||
reg [DATA_WIDTH - 1:0] regx_in_data [WINDOWS_WIDTH-1];
|
||||
reg [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
|
||||
reg [WINDOWS_WIDTH - 2:0] regx_in_valid, regx_out_valid;
|
||||
|
||||
reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
|
||||
|
||||
|
||||
/* outdata[x]:
|
||||
SHIFT_REG1 -> 0 3 6 . .
|
||||
SHIFT_REG0 -> 1 4 7 . .
|
||||
in_data -> 2 5 8 . .
|
||||
. . .
|
||||
. . .
|
||||
*/
|
||||
|
||||
reg [15:0] pos_x, pos_y;
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
pos_x <= 0;
|
||||
pos_y <= 0;
|
||||
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
|
||||
pos_x <= (pos_x >= IMAGE_WIDTH - 1) ? (0) : (pos_x + 1);
|
||||
pos_y <= (pos_x >= IMAGE_WIDTH - 1)?((pos_y >= IMAGE_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
|
||||
end else begin
|
||||
pos_x <= pos_x;
|
||||
pos_y <= pos_y;
|
||||
end
|
||||
end
|
||||
|
||||
integer i, j;
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH; i = i + 1) out_data[i] <= 0;
|
||||
out_valid <= 0;
|
||||
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
|
||||
for (i = 0; i < WINDOWS_WIDTH; i = i + 1) begin
|
||||
for (j = 0; j < WINDOWS_WIDTH; j = j + 1) begin
|
||||
if (i == WINDOWS_WIDTH - 1) begin
|
||||
if (j == 0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
|
||||
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*i-1];
|
||||
end else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
|
||||
end
|
||||
end
|
||||
out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
|
||||
end else begin
|
||||
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH - 1; i = i + 1) out_data[i] <= out_data[i];
|
||||
out_valid <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset)
|
||||
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1)
|
||||
for (j = 0; j < WINDOWS_WIDTH - 1; j = j + 1) data_out_shift[i][j] <= 0;
|
||||
else
|
||||
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
|
||||
for (j = 0; j < 2 * (WINDOWS_WIDTH - 1); j = j + 1) begin
|
||||
if (i == WINDOWS_WIDTH - 2 && j == 0) data_out_shift[i][j] <= in_data;
|
||||
else if (j == 0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
|
||||
else data_out_shift[i][j] <= data_out_shift[i][j-1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
|
||||
if (i == 0) regx_in_data[i] = in_data;
|
||||
else regx_in_data[i] = regx_out_data[i-1];
|
||||
end
|
||||
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
|
||||
if (i == 0) regx_in_valid[i] = in_valid;
|
||||
else regx_in_valid[i] = regx_out_valid[i-1];
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
genvar o;
|
||||
for (o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin : shift_register
|
||||
SHIFT_REGISTER #(
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
.IMAGE_WIDTH(IMAGE_WIDTH),
|
||||
.IFOUTIMME (1'b1)
|
||||
) shift_registerx (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_data (regx_in_data[o]),
|
||||
.out_data (regx_out_data[o]),
|
||||
.in_valid (regx_in_valid[o]),
|
||||
.out_valid(regx_out_valid[o])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user