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add pipeline and pass sim

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SikongJueluo
2024-10-22 20:31:51 +08:00
parent f4efa6177e
commit 1ab1467569
18 changed files with 848 additions and 957 deletions
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298
rtl/BayerProcess/DPC.sv Normal file
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`timescale 1ns / 1ps
module DPC #(
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
) (
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [5*5],
output reg [DATA_WIDTH - 1:0] out_data,
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready
);
localparam WINDOW_LENGTH = 5;
localparam DATA_NUM = WINDOW_LENGTH * WINDOW_LENGTH;
localparam EXPAND_BITS = 5;
localparam PIPILINE = 9;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点
reg [DATA_WIDTH-1:0]
channel_cache0,
channel_cache1,
channel_cache2,
channel_cache3,
channel_cache4; // 缓存中心像素点的颜色数据
reg signed [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache[3], grad_v_cache[3], grad_45_cache[3], grad_135_cache[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache0[3], grad_v_cache0[3], grad_45_cache0[3], grad_135_cache0[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache1[3], grad_v_cache1[3], grad_45_cache1[3], grad_135_cache1[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache2[3], grad_v_cache2[3], grad_45_cache2[3], grad_135_cache2[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
reg [1:0] flag_which_dict;
reg [DATA_WIDTH-1:0]
channel_cache_correct[4],
channel_cache_correct0[4],
channel_cache_correct1[4],
channel_cache_correct2[4];
reg [DATA_WIDTH-1:0] channel_cache_correct_final;
reg flag_if_need_corection;
reg [15:0] pos_x;
reg pos_y_bit;
reg [1:0] raw_type;
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0;
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0;
for (i = 0; i < 9; i = i + 1) channel_cache[i] <= 0;
channel_cache0 <= 0;
channel_cache1 <= 0;
channel_cache2 <= 0;
channel_cache3 <= 0;
channel_cache4 <= 0;
channel_cache_correct_final <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_median_cache[i] <= 0;
flag_which_dict <= 0;
flag_if_need_corection <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct0[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= 0;
pipeline_valid <= 0;
out_data <= 0;
pos_x <= ~0;
pos_y_bit <= ~0;
raw_type <= RAW_TYPE;
end else if (pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i];
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y_bit <= (pos_x >= TOTAL_WIDTH - 1) ? (~pos_y_bit) : (pos_y_bit);
end
if (pipeline_valid[0]) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i];
case (RAW_TYPE)
2'b00: raw_type <= {pos_y_bit, pos_x[0]};
2'b01: raw_type <= {pos_y_bit, ~pos_x[0]};
2'b10: raw_type <= {~pos_y_bit, pos_x[0]};
2'b11: raw_type <= {~pos_y_bit, ~pos_x[0]};
endcase
end
if (pipeline_valid[1]) begin
case (raw_type)
1, 2: begin
channel_cache[0] <= data_cache[00];
channel_cache[1] <= data_cache[10];
channel_cache[2] <= data_cache[20];
channel_cache[3] <= data_cache[02];
channel_cache[4] <= data_cache[12];
channel_cache[5] <= data_cache[22];
channel_cache[6] <= data_cache[04];
channel_cache[7] <= data_cache[14];
channel_cache[8] <= data_cache[24];
end
0, 3: begin
channel_cache[0] <= data_cache[02];
channel_cache[1] <= data_cache[06];
channel_cache[2] <= data_cache[10];
channel_cache[3] <= data_cache[08];
channel_cache[4] <= data_cache[12];
channel_cache[5] <= data_cache[16];
channel_cache[6] <= data_cache[14];
channel_cache[7] <= data_cache[18];
channel_cache[8] <= data_cache[22];
end
endcase
end
if (pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算
channel_cache0 <= channel_cache[4];
grad_h_cache[0] <= channel_cache[0] + channel_cache[2] - 2 * channel_cache[1];
grad_h_cache[1] <= channel_cache[3] + channel_cache[5] - 2 * channel_cache[4];
grad_h_cache[2] <= channel_cache[6] + channel_cache[8] - 2 * channel_cache[7];
grad_v_cache[0] <= channel_cache[0] + channel_cache[6] - 2 * channel_cache[3];
grad_v_cache[1] <= channel_cache[1] + channel_cache[7] - 2 * channel_cache[4];
grad_v_cache[2] <= channel_cache[2] + channel_cache[8] - 2 * channel_cache[5];
grad_45_cache[0] <= 2 * (channel_cache[1] - channel_cache[3]);
grad_45_cache[1] <= channel_cache[6] + channel_cache[2] - 2 * channel_cache[4];
grad_45_cache[2] <= 2 * (channel_cache[7] - channel_cache[5]);
grad_135_cache[0] <= 2 * (channel_cache[1] - channel_cache[5]);
grad_135_cache[1] <= channel_cache[0] + channel_cache[8] - 2 * channel_cache[4];
grad_135_cache[2] <= 2 * (channel_cache[3] - channel_cache[7]);
channel_cache_correct[0] <= channel_cache[3] / 2 + channel_cache[5] / 2;
channel_cache_correct[1] <= channel_cache[1] / 2 + channel_cache[7] / 2;
channel_cache_correct[2] <= channel_cache[2] / 2 + channel_cache[6] / 2;
channel_cache_correct[3] <= channel_cache[0] / 2 + channel_cache[8] / 2;
end
if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算,注意grad_h_cache等是singed，可能为负数
channel_cache1 <= channel_cache0;
grad_h_cache0 [0] <= grad_h_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [0] + 1) : (grad_h_cache [0]);
grad_h_cache0 [1] <= grad_h_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [1] + 1) : (grad_h_cache [1]);
grad_h_cache0 [2] <= grad_h_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [2] + 1) : (grad_h_cache [2]);
grad_v_cache0 [0] <= grad_v_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [0] + 1) : (grad_v_cache [0]);
grad_v_cache0 [1] <= grad_v_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [1] + 1) : (grad_v_cache [1]);
grad_v_cache0 [2] <= grad_v_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [2] + 1) : (grad_v_cache [2]);
grad_45_cache0 [0] <= grad_45_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [0] + 1) : (grad_45_cache [0]);
grad_45_cache0 [1] <= grad_45_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [1] + 1) : (grad_45_cache [1]);
grad_45_cache0 [2] <= grad_45_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [2] + 1) : (grad_45_cache [2]);
grad_135_cache0[0] <= grad_135_cache[0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[0] + 1) : (grad_135_cache[0]);
grad_135_cache0[1] <= grad_135_cache[1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[1] + 1) : (grad_135_cache[1]);
grad_135_cache0[2] <= grad_135_cache[2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[2] + 1) : (grad_135_cache[2]);
channel_cache_correct0[0] <= channel_cache_correct[0] + grad_h_cache[0]/4 + grad_h_cache[2]/4;
channel_cache_correct0[1] <= channel_cache_correct[1] + grad_v_cache[0]/4 + grad_v_cache[2]/4;
channel_cache_correct0[2] <= channel_cache_correct[2] + grad_45_cache[0]/4 + grad_45_cache[2]/4;
channel_cache_correct0[3] <= channel_cache_correct[3] + grad_135_cache[0]/4 + grad_135_cache[2]/4;
end
if (pipeline_valid[4]) begin //计算中位数
channel_cache2 <= channel_cache1;
for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= channel_cache_correct0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache1[i] <= grad_h_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache1[i] <= grad_v_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache1[i] <= grad_45_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache1[i] <= grad_135_cache0[i];
grad_median_cache[0] <= MEDIAN(grad_h_cache0);
grad_median_cache[1] <= MEDIAN(grad_v_cache0);
grad_median_cache[2] <= MEDIAN(grad_45_cache0);
grad_median_cache[3] <= MEDIAN(grad_135_cache0);
end
if (pipeline_valid[5]) begin //计算最小值，判断最小梯度方向
channel_cache3 <= channel_cache2;
for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= channel_cache_correct1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache2[i] <= grad_h_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache2[i] <= grad_v_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache2[i] <= grad_45_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache2[i] <= grad_135_cache1[i];
flag_which_dict <= MIN(grad_median_cache);
end
if (pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点
channel_cache4 <= channel_cache3;
channel_cache_correct_final <= channel_cache_correct2[flag_which_dict];
case (flag_which_dict)
2'b00:
flag_if_need_corection <= grad_h_cache2[1] > 4 * (grad_h_cache2[0] + grad_h_cache2[2]);
2'b01:
flag_if_need_corection <= grad_v_cache2[1] > 4 * (grad_v_cache2[0] + grad_v_cache2[2]);
2'b10:
flag_if_need_corection <= grad_45_cache2[1] > 3 * (grad_45_cache2[0] + grad_45_cache2[2]);
2'b11:
flag_if_need_corection <= grad_135_cache2[1] > 3*(grad_135_cache2[0] + grad_135_cache2[2]);
endcase
end
if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值
out_data <= (flag_if_need_corection) ? (channel_cache_correct_final) : (channel_cache4);
end
end
end
function [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN;
input [DATA_WIDTH-1+EXPAND_BITS:0] inx[3];
begin
if ((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0]))
MEDIAN = inx[1];
else if ((inx[1] >= inx[0]) || (inx[0] >= inx[1])) MEDIAN = inx[0];
else MEDIAN = inx[2];
end
endfunction
function [1:0] MIN;
input [DATA_WIDTH-1+EXPAND_BITS:0] inx[4];
begin
if (inx[0] >= inx[1] && inx[0] >= inx[2] && inx[0] >= inx[3]) MIN = 2'b00;
else if (inx[1] >= inx[0] && inx[1] >= inx[2] && inx[1] >= inx[3]) MIN = 2'b01;
else if (inx[2] >= inx[0] && inx[2] >= inx[1] && inx[2] >= inx[3]) MIN = 2'b10;
else MIN = 2'b11;
end
endfunction
/*
00 05 10 15 20
01 06 11 16 21 0 1 2
02 07 12 17 22 -> 3 4 5
03 08 13 18 23 6 7 8
04 09 14 19 24
rawtype==0: center is GREEN
g r g r g / / g / /
b g b g b / g / g /
g r g r g -> g / G / g
b g b g b / g / g /
g r g r g / / g / /
rawtype==1: center is RED
r g r g r r / r / r
g b g b g / / / / /
r g r g r -> r / R / r
g b g b g / / / / /
r g r g r r / r / r
rawtype==2: center is BLUE
b g b g b b / b / b
g r g r g / / / / /
b g b g b -> b / B / b
g r g r g / / / / /
b g b g b b / b / b
rawtype==3: center is GREEN
g b g b g / / g / /
r g r g r / g / g /
g b g b g -> g / G / g
r g r g r / g / g /
r g r g r / / g / /
*/
endmodule

0
rtl/Demosaic/Demosaic2.sv → rtl/BayerProcess/Demosaic2.sv
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121
rtl/BayerProcess/Demosaic_Pipeline.sv Normal file
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`timescale 1ns / 1ps
module Demosaic_Pipeline #(
parameter WINDOW_LENGTH = 3,
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
) (
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
output reg [DATA_WIDTH - 1:0] out_data[3], // 数据输出线，3、2、1分别表示r、g、b
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
);
localparam DATA_NUM = WINDOW_LENGTH * WINDOW_LENGTH;
localparam PIPILINE = 4;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache [DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [31:0] pos_x, pos_y, temp_pos_x1, temp_pos_y1, temp_pos_x2, temp_pos_y2;
reg [DATA_WIDTH-1:0] red, blue, green;
reg [1:0] raw_type;
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0;
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0;
pipeline_valid <= 0;
{red, green, blue} <= 0;
{out_data[2], out_data[1], out_data[0]} <= 0;
{out_hsync, out_fsync} <= 0;
pos_x <= ~0;
pos_y <= ~0;
temp_pos_x1 <= ~0;
temp_pos_y1 <= ~0;
temp_pos_x2 <= ~0;
temp_pos_y2 <= ~0;
raw_type <= RAW_TYPE;
end else if (pipeline_running) begin
// First level pipeline for reading data
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i];
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
end
if (pipeline_valid[0]) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i];
temp_pos_x1 <= pos_x;
temp_pos_y1 <= pos_y;
case (RAW_TYPE)
2'b00: raw_type <= {pos_y[0], pos_x[0]};
2'b01: raw_type <= {pos_y[0], ~pos_x[0]};
2'b10: raw_type <= {~pos_y[0], pos_x[0]};
2'b11: raw_type <= {~pos_y[0], ~pos_x[0]};
endcase
end
if (pipeline_valid[1]) begin
temp_pos_x2 <= temp_pos_x1;
temp_pos_y2 <= temp_pos_y1;
case (raw_type)
0: begin // Missing B, R on G
blue <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
red <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
green <= data_cache[4];
end
1: begin // Missing G, R on B
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
red <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
blue <= data_cache[4];
end
2: begin // Missing G, B on R
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
blue <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
red <= data_cache[4];
end
3: begin // Missing B, R on G
red <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
blue <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
green <= data_cache[4];
end
endcase
end
if (pipeline_valid[2]) begin
{out_data[2], out_data[1], out_data[0]} <= {red, blue, green};
out_hsync <= (temp_pos_x2 == 0);
out_fsync <= ((temp_pos_x2 == 0) && (temp_pos_y2 == 0));
end
end
end
// 0:grg 1:rgr 2:bgb 3:gbg 036 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
// bgb gbg grg rgr 147
// grg rgr bgb gbg 258
endmodule

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rtl/BayerProcess/Gowin_SDPB.sv Normal file
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//Gowin SDPB IP<49>˷<EFBFBD><CBB7><EFBFBD><EFBFBD>ļ<EFBFBD>
`timescale 1ns / 1ps
module Gowin_SDPB (
input wire clka,
input wire clkb, //no use
input wire reset,
input wire cea,
input wire ceb,
input wire [10:0] ada,
input wire [10:0] adb,
input wire [15:0] din,
output reg [15:0] dout,
input wire oce //no use
);
reg [15:0] bram[2048];
integer i;
initial for (i = 0; i < 2048; i = i + 1) bram[i] = 0;
always @(posedge clka) begin
if (reset) for (i = 0; i < 2048; i = i + 1) bram[i] <= 0;
else if (cea) bram[ada] <= din;
end
always @(posedge clka) begin
if (reset) dout <= 0;
else if (ceb) dout <= bram[adb];
end
endmodule

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rtl/BayerProcess/SHIFT_REGISTER.sv Normal file
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//RAM-BASED移位寄存器
`timescale 1ns / 1ps
module SHIFT_REGISTER #(
parameter reg [4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter IMAGE_WIDTH = 1936, //MAX 2048
parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满
) (
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [DATA_WIDTH - 1:0] in_data,
output wire [DATA_WIDTH - 1:0] out_data,
// 有效信号
input wire in_valid, // 上一模块输出数据有效
output wire out_valid // 当前模块输出数据有效
);
reg [10:0] addr_a, addr_b;
wire cea, ceb;
reg fulldone;
reg in_valid_temp0, in_valid_temp1;
always @(posedge clk) in_valid_temp0 <= in_valid && (fulldone || IFOUTIMME);
always @(posedge clk) in_valid_temp1 <= in_valid_temp0;
assign cea = in_valid;
assign ceb = in_valid_temp0;
assign out_valid = in_valid_temp1;
always @(posedge clk) begin
if (reset) fulldone <= 0;
else if (addr_b == IMAGE_WIDTH - 1) fulldone <= 1;
else fulldone <= fulldone;
end
always @(posedge clk) begin
if (reset) begin
addr_a <= IMAGE_WIDTH + 1;
addr_b <= 0;
end else if (cea) begin
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end else begin
addr_a <= addr_a;
addr_b <= addr_b;
end
end
// Single-Double-Port-BRAM-IP Bypass Normal
Gowin_SDPB Gowin_SDPB_inst (
.clka (clk), //input clka
.clkb (clk), //input clkb
.reset(reset), //input reset
.cea(cea), //input cea
.ceb(ceb), //input ceb
.ada(addr_a), //input [10:0] ada
.adb(addr_b), //input [10:0] adb
.din (in_data), //input [15:0] din
.dout(out_data), //output [15:0] dout
.oce(1) //input oce
);
endmodule

119
rtl/BayerProcess/Windows.sv Normal file
View File

@@ -0,0 +1,119 @@
`timescale 1ns / 1ps
module Windows #(
parameter DATA_WIDTH = 16,
parameter IMAGE_WIDTH = 1936,
parameter IMAGE_HEIGHT = 1088,
parameter WINDOWS_WIDTH = 3,
parameter WINDOWS_ANCHOR_X = 1, //禁止大于WINDOWS_WIDTH-1
parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1
) (
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [DATA_WIDTH - 1:0] in_data,
output reg [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线
// 有效信号
input wire in_valid, // 上一模块输出数据有效
output reg out_valid, // 当前模块输出数据有效
// 准备信号 Windows模块无法停止，因此默认不处理准备信号
input wire in_ready,
output wire out_ready
);
assign out_ready = 1'b1;
reg [DATA_WIDTH - 1:0] regx_in_data [WINDOWS_WIDTH-1];
reg [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
reg [WINDOWS_WIDTH - 2:0] regx_in_valid, regx_out_valid;
reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
/* outdata[x]:
SHIFT_REG1 -> 0 3 6 . .
SHIFT_REG0 -> 1 4 7 . .
in_data -> 2 5 8 . .
. . .
. . .
*/
reg [15:0] pos_x, pos_y;
always @(posedge clk) begin
if (reset) begin
pos_x <= 0;
pos_y <= 0;
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
pos_x <= (pos_x >= IMAGE_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y <= (pos_x >= IMAGE_WIDTH - 1)?((pos_y >= IMAGE_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
end else begin
pos_x <= pos_x;
pos_y <= pos_y;
end
end
integer i, j;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH; i = i + 1) out_data[i] <= 0;
out_valid <= 0;
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
for (i = 0; i < WINDOWS_WIDTH; i = i + 1) begin
for (j = 0; j < WINDOWS_WIDTH; j = j + 1) begin
if (i == WINDOWS_WIDTH - 1) begin
if (j == 0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*i-1];
end else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
end
end
out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
end else begin
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH - 1; i = i + 1) out_data[i] <= out_data[i];
out_valid <= 0;
end
end
always @(posedge clk) begin
if (reset)
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1)
for (j = 0; j < WINDOWS_WIDTH - 1; j = j + 1) data_out_shift[i][j] <= 0;
else
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
for (j = 0; j < 2 * (WINDOWS_WIDTH - 1); j = j + 1) begin
if (i == WINDOWS_WIDTH - 2 && j == 0) data_out_shift[i][j] <= in_data;
else if (j == 0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
else data_out_shift[i][j] <= data_out_shift[i][j-1];
end
end
end
always @(*) begin
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
if (i == 0) regx_in_data[i] = in_data;
else regx_in_data[i] = regx_out_data[i-1];
end
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
if (i == 0) regx_in_valid[i] = in_valid;
else regx_in_valid[i] = regx_out_valid[i-1];
end
end
generate
genvar o;
for (o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin : shift_register
SHIFT_REGISTER #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.IFOUTIMME (1'b1)
) shift_registerx (
.clk (clk),
.reset (reset),
.in_data (regx_in_data[o]),
.out_data (regx_out_data[o]),
.in_valid (regx_in_valid[o]),
.out_valid(regx_out_valid[o])
);
end
endgenerate
endmodule

27
rtl/Color/ColorBlender_Pipeline.sv
View File

@@ -2,24 +2,24 @@
// 三通道图像合成一个RGB图像
module ColorBlender_Pipeline #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] DATA_WIDTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
input wire [DATA_WIDTH - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
@@ -29,7 +29,6 @@ module ColorBlender_Pipeline #(
input wire [15:0] gain_blue,
input wire enable
);
localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
@@ -65,9 +64,9 @@ module ColorBlender_Pipeline #(
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[0] <= (in_data[0]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[1] <= (in_data[1]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[2] <= (in_data[2]) << (8 - (DATA_WIDTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
@@ -83,9 +82,9 @@ module ColorBlender_Pipeline #(
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
data_cal2[0] <= (|data_cal1[0][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (|data_cal1[1][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (|data_cal1[2][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin

85
rtl/Color/GammaCorrection_Pipeline.sv Executable file
View File

@@ -0,0 +1,85 @@
`timescale 1ns / 1ps
module GammaCorrection_Pipeline #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_valid,
output reg out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
output wire out_hsync,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
input wire [7:0] gamma_table[256],
input wire enable
);
reg [7:0] data_cache[3];
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk)
begin
if (reset)
begin
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
end
else
begin
case (state)
READ_DATA:
begin
if (in_en)
begin
data_cache[0] <= in_data[0];
data_cache[1] <= in_data[1];
data_cache[2] <= in_data[2];
end
end
SEND_DATA:
begin
if (in_ready && !in_receive)
begin
out_en <= 1;
if (enable)
begin
out_data[0] <= gamma_table[data_cache[0]];
out_data[1] <= gamma_table[data_cache[1]];
out_data[2] <= gamma_table[data_cache[2]];
end
else
begin
out_data[0] <= data_cache[0];
out_data[1] <= data_cache[1];
out_data[2] <= data_cache[2];
end
end
else
out_en <= 0;
end
default:
;
endcase
end
end
endmodule

132
rtl/Demosaic/Demosaic_Pipeline.sv
View File

@@ -1,132 +0,0 @@
`timescale 1ns / 1ps
module Demosaic_Pipeline #(
parameter WINDOW_LENGTH = 3,
parameter reg [15:0] TOTAL_WIDTH = 512+3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256+3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
)(
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
);
localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [31:0] pos_x, pos_y, temp_pos_x, temp_pos_y;
reg [DATA_WIDTH-1:0] red, blue, green;
reg [1:0] raw_type;
integer i;
always @(posedge clk)
begin
if(reset)
begin
for(i=0;i<DATA_NUM;i=i+1)
data_cache[i] <= 0;
pipeline_valid <= 0;
{red, green, blue} <= 0;
{out_data[2],out_data[1],out_data[0]} <= 0;
{out_hsync,out_fsync} <= 0;
pos_x <= ~0;
pos_y <= ~0;
temp_pos_x <= 0;
temp_pos_y <= 0;
end
else if(pipeline_running)
begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if(in_valid)
begin
for(i=0;i<DATA_NUM;i=i+1)
data_cache[i] <= in_data[i];
pos_x <= (pos_x >= TOTAL_WIDTH - 1)?(0):(pos_x + 1);
pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
end
if(pipeline_valid[0])
begin
temp_pos_x <= pos_x;
temp_pos_y <= pos_y;
case (raw_type)
0:
begin // Missing B, R on G
blue <= (data_cache[1] + data_cache[7]) >> 1;
red <= (data_cache[3] + data_cache[5]) >> 1;
green <= data_cache[4];
end
1:
begin // Missing G, R on B
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
red <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
blue <= data_cache[4];
end
2:
begin // Missing G, B on R
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
blue <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
red <= data_cache[4];
end
3:
begin // Missing B, R on G
red <= (data_cache[1] + data_cache[7]) >> 1;
blue <= (data_cache[3] + data_cache[5]) >> 1;
green <= data_cache[4];
end
endcase
end
if(pipeline_valid[1])
begin
{out_data[2],out_data[1],out_data[0]} <= {red,blue,green};
out_hsync <= (temp_pos_x == 0);
out_fsync <= ((temp_pos_x == 0) && (temp_pos_y == 0));
end
end
end
// 0:gr 1:rg 2:bg 3:gb 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
// bg gb gr rg
always @(*)
begin
if(reset)
raw_type = RAW_TYPE;
else
case (RAW_TYPE)
2'b00:
raw_type = {pos_y[0], pos_x[0]};
2'b01:
raw_type = {pos_y[0], ~pos_x[0]};
2'b10:
raw_type = {~pos_y[0], pos_x[0]};
2'b11:
raw_type = {~pos_y[0], ~pos_x[0]};
endcase
end
endmodule

56
rtl/Demosaic/Windows.sv
View File

@@ -1,56 +0,0 @@
`timescale 1ns / 1ps
module Windows #(
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
)(
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [DATA_WIDTH - 1:0] in_data [3], // 0、1、2分别表示第一、二、三行
output reg [DATA_WIDTH - 1:0] out_data [3*3], // 数据输出线
// 有效信号
input wire in_valid, // 上一模块输出数据有效
output wire out_valid, // 当前模块输出数据有效
// 准备信号
input wire in_ready, // 下一模块可接受新数据
output wire out_ready // 当前模块可接收新数据
);
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = (pipeline_valid != {PIPILINE{1'b1}}) | ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready);
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid == {PIPILINE{1'b1}});
integer i;
always @(posedge clk) begin
if(reset) begin
for(i=0;i<9;i=i+1) out_data[i] <= 0;
pipeline_valid <= 0;
end else begin
if((pipeline_valid != {PIPILINE{1'b1}}) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
pipeline_valid[0] <= in_valid;
out_data[6] <= in_data[0];
out_data[7] <= in_data[1];
out_data[8] <= in_data[2];
end
if((pipeline_valid[2] == 0) || (pipeline_valid[1] == 0) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
pipeline_valid[1] <= pipeline_valid[0];
out_data[3] <= out_data[6];
out_data[4] <= out_data[7];
out_data[5] <= out_data[8];
end
if((pipeline_valid[2] == 0) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
pipeline_valid[2] <= pipeline_valid[1];
out_data[0] <= out_data[3];
out_data[1] <= out_data[4];
out_data[2] <= out_data[5];
end
end
end
endmodule

114
rtl/isp_Pipeline.sv
View File

@@ -1,6 +1,13 @@
`timescale 1ns / 1ps
/* TODO 1. ISP寄存器配置模式，如配置是否启用什么什么矫正，矫正系数多少。能读能写。选好通信协议，要不要用AXI？
2. 白平衡，GAMMA矫正。白平衡做RAW白平衡吗？
3. 寄存器中应该有一个寄存器标识ISP运行状态。比如裁切模块，直接修改寄存器值数据就乱了。
4. 缩放模块。如何处理模块进出数据量不匹配？
5. 旋转模块。这怎么做？
6. ISP不应该只有一条线，比如存进SDRAM后，读出来时也可以做处理。
*/
module isp_Pipeline #(
parameter reg [15:0] DATA_WIDTH = 12,
parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088,
parameter OFFSET_X = 7,
@@ -15,8 +22,10 @@ module isp_Pipeline #(
input wire reset,
// 数据线
input wire [15:0] in_data[3], // 数据输入线，0、1、2分别表示第一、二、三行
input wire [DATA_WIDTH-1:0] in_data, // 数据输入线
output wire [3 * COLOR_DEPTH - 1:0] out_data,
output wire fsync,
output wire hsync,
// 数据有效信号
input wire in_valid,
@@ -33,29 +42,70 @@ module isp_Pipeline #(
input wire blender_enable // 是否启用颜色校正
);
wire [15:0] Demosaic2_data[3];
wire [15:0] Windows_data[9];
wire [DATA_WIDTH-1:0] DPC_data;
wire [DATA_WIDTH-1:0] Demosaic_data[3];
wire [DATA_WIDTH-1:0] Windows_DPC_data[5*5];
wire [DATA_WIDTH-1:0] Windows_Demosaic_data[3*3];
wire [COLOR_DEPTH - 1 : 0] Blender_data[3];
wire [COLOR_DEPTH - 1 : 0] Crop_data[3];
wire Windows_valid, Demosaic2_valid, Blender_valid, Crop_valid;
wire Windows_ready, Demosaic2_ready, Blender_ready, Crop_ready;
wire Demosaic2_hsync, Blender_hsync, Crop_hsync;
wire Demosaic2_fsync, Blender_fsync, Crop_fsync;
wire Windows_DPC_valid, DPC_valid, Windows_Demosaic_valid, Demosaic_valid, Blender_valid, Crop_valid;
wire Windows_DPC_ready, DPC_ready, Windows_Demosaic_ready, Demosaic_ready, Blender_ready, Crop_ready;
wire Demosaic_hsync, Blender_hsync, Crop_hsync;
wire Demosaic_fsync, Blender_fsync, Crop_fsync;
assign out_valid = Crop_valid;
assign out_ready = Windows_ready;
assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]};
assign out_ready = Windows_DPC_ready;
assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]};
assign fsync = Crop_fsync;
assign hsync = Crop_hsync;
Windows #(
.DATA_WIDTH(16)
) Windows_inst (
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IN_WIDTH),
.WINDOWS_WIDTH (5),
.WINDOWS_ANCHOR_X(2),
.WINDOWS_ANCHOR_Y(2)
) Windows_DPC_inst (
.clk (clk),
.reset (reset),
.in_data (in_data),
.out_data (Windows_data),
.out_data (Windows_DPC_data),
.in_valid (in_valid),
.out_valid(Windows_valid),
.in_ready (Demosaic2_ready),
.out_ready(Windows_ready)
.out_valid(Windows_DPC_valid),
.in_ready (DPC_ready),
.out_ready(Windows_DPC_ready)
);
DPC #(
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT(IN_HEIGHT),
.RAW_TYPE (3),
.DATA_WIDTH (DATA_WIDTH)
) DPC_inst (
.clk (clk),
.reset (reset),
.in_data (Windows_DPC_data),
.out_data (DPC_data),
.in_valid (Windows_DPC_valid),
.out_valid(DPC_valid),
.in_ready (Windows_Demosaic_ready),
.out_ready(DPC_ready)
);
Windows #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IN_WIDTH),
.WINDOWS_WIDTH (3),
.WINDOWS_ANCHOR_X(1),
.WINDOWS_ANCHOR_Y(1)
) Windows_Demosaic_inst (
.clk (clk),
.reset (reset),
.in_data (DPC_data),
.out_data (Windows_Demosaic_data),
.in_valid (DPC_valid),
.out_valid(Windows_Demosaic_valid),
.in_ready (Demosaic_ready),
.out_ready(Windows_Demosaic_ready)
);
@@ -63,35 +113,35 @@ module isp_Pipeline #(
.WINDOW_LENGTH(3),
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (RAW_TYPE),
.DATA_WIDTH (16)
) Demosaic2_inst (
.RAW_TYPE (3),
.DATA_WIDTH (DATA_WIDTH)
) Demosaic_inst (
.clk (clk),
.reset (reset),
.in_data (Windows_data),
.out_data (Demosaic2_data),
.in_valid (Windows_valid),
.out_valid(Demosaic2_valid),
.in_data (Windows_Demosaic_data),
.out_data (Demosaic_data),
.in_valid (Windows_Demosaic_valid),
.out_valid(Demosaic_valid),
.in_ready (Blender_ready),
.out_ready(Demosaic2_ready),
.out_hsync(Demosaic2_hsync),
.out_fsync(Demosaic2_fsync)
.out_ready(Demosaic_ready),
.out_hsync(Demosaic_hsync),
.out_fsync(Demosaic_fsync)
);
ColorBlender_Pipeline #(
.IN_DEPTH(12), // 输入图像的色深
.OUT_DEPTH(COLOR_DEPTH) // 输出图像的色深
.DATA_WIDTH(DATA_WIDTH), // 输入图像的色深
.OUT_DEPTH (COLOR_DEPTH) // 输出图像的色深
) ColorBlender_inst (
.clk (clk),
.reset (reset),
.in_data (Demosaic2_data),
.in_data (Demosaic_data),
.out_data (Blender_data),
.in_valid (Demosaic2_valid),
.in_valid (Demosaic_valid),
.out_valid(Blender_valid),
.in_ready (Crop_ready),
.out_ready(Blender_ready),
.in_hsync (Demosaic2_hsync),
.in_fsync (Demosaic2_fsync),
.in_hsync (Demosaic_hsync),
.in_fsync (Demosaic_fsync),
.out_hsync(Blender_hsync),
.out_fsync(Blender_fsync),