40 lines
827 B
Systemverilog
40 lines
827 B
Systemverilog
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`timescale 1ns / 1ps
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// 三通道图像合成一个RGB图像
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module WhiteBalance #(
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parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
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parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
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parameter reg [8:0] BUFF_SIZE = 32
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) (
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input wire clk,
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input wire reset,
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input wire in_en,
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input wire [15:0] in_data[3], // 0:R 1:G 2:B
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output wire out_ready,
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output wire out_receive,
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// 输出相关
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input wire in_ready,
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input wire in_receive,
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output reg out_en,
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output reg [OUT_DEPTH - 1:0] out_data[3],
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input wire enable,
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input wire [8:0] flame_rate
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);
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assign out_ready = (!reset) ? 1 : 0;
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assign out_receive = (in_en && !reset) ? 1 : 0;
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DiffWidthSyncFIFO #(
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)
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always @(posedge clk) begin
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if(reset) begin
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end
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end
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endmodule
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