SikongJueluo 8bcad1f23f refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation ...

- Extract cam_bank as a parameterized submodule with independent read/write ports
- Replace flat 2D memory array with generate loop of bank instances
- Derive bank selection from address bit slicing instead of modulo arithmetic
- Align rd_base_row_i check with new bank addressing scheme
- Add test verifying bank address isolation across multiple banks

2026-05-19 16:17:08 +08:00

..

cam_core_banked

refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation

2026-05-19 16:17:08 +08:00

cam_read_noise

refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

2026-05-16 19:24:17 +08:00

cam_write_noise

refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

2026-05-16 19:24:17 +08:00

match_engine_pipeline

refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

2026-05-16 19:24:17 +08:00

popcount_pipeline

test(popcount_pipeline): add cocotb test for popcount pipeline module

2026-05-18 15:37:26 +08:00

__init__.py

refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

2026-05-16 19:24:17 +08:00