SikongJueluo 8bcad1f23f refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation ...

- Extract cam_bank as a parameterized submodule with independent read/write ports
- Replace flat 2D memory array with generate loop of bank instances
- Derive bank selection from address bit slicing instead of modulo arithmetic
- Align rd_base_row_i check with new bank addressing scheme
- Add test verifying bank address isolation across multiple banks

2026-05-19 16:17:08 +08:00

..

rtl

refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation

2026-05-19 16:17:08 +08:00

sim

refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation

2026-05-19 16:17:08 +08:00

syn

feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility

2026-05-18 15:40:04 +08:00

.gitignore

feat(sim): enable read noise by default and improve test infrastructure

2026-05-17 14:11:59 +08:00