SikongJueluo 8bcad1f23f refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation
- Extract cam_bank as a parameterized submodule with independent read/write ports
- Replace flat 2D memory array with generate loop of bank instances
- Derive bank selection from address bit slicing instead of modulo arithmetic
- Align rd_base_row_i check with new bank addressing scheme
- Add test verifying bank address isolation across multiple banks
2026-05-19 16:17:08 +08:00
2026-05-15 14:03:40 +08:00
2026-01-19 15:24:36 +08:00
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