3 Commits

Author	SHA1	Message	Date
SikongJueluo	8bcad1f23f	refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation ... - Extract cam_bank as a parameterized submodule with independent read/write ports - Replace flat 2D memory array with generate loop of bank instances - Derive bank selection from address bit slicing instead of modulo arithmetic - Align rd_base_row_i check with new bank addressing scheme - Add test verifying bank address isolation across multiple banks	2026-05-19 16:17:08 +08:00
SikongJueluo	b9b5684718	test(popcount_pipeline): add cocotb test for popcount pipeline module ... - Add Makefile with cocotb configuration for popcount_pipeline RTL simulation - Add Python test module with reset, drive/expect helpers - Test row metadata preservation and bit-count correctness across 7 vectors	2026-05-18 15:37:26 +08:00
SikongJueluo	ca167e79c6	refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory ... - Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk) - Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top) - Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix - Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware	2026-05-16 19:24:17 +08:00