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SikongJueluo
706d148a0b
- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function
78 lines
2.4 KiB
Systemverilog
78 lines
2.4 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_write_noise #(
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter int WRITE_NOISE_BITS = 8,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D
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) (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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output logic core_wr_valid,
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output logic [(`ROW_BITS)-1:0] core_wr_row,
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output logic [(`HASH_BITS)-1:0] core_wr_hash
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);
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logic pending_q;
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logic [(`ROW_BITS)-1:0] row_q;
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logic [(`HASH_BITS)-1:0] hash_q;
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logic [127:0] random_num;
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logic [(`HASH_BITS)-1:0] flip_mask;
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assign wr_ready = !pending_q;
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random128 u_random_write (
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.clk (clk),
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.rst_n (rst_n),
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.enable(wr_valid && wr_ready && WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)),
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.seed ({WRITE_NOISE_SEED, WRITE_NOISE_SEED}),
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.out (random_num)
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);
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noise_mask_grouped #(
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.HASH_BITS (`HASH_BITS),
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.NOISE_BITS (WRITE_NOISE_BITS),
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.NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
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.NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN)
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) u_mask (
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.random_i(random_num),
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.mask_o (flip_mask)
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);
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`ifndef SYNTHESIS
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initial begin
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if (WRITE_NOISE_SEED == 64'd0) $fatal(1, "WRITE_NOISE_SEED must be nonzero");
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end
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`endif
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pending_q <= 1'b0;
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row_q <= '0;
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hash_q <= '0;
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core_wr_valid <= 1'b0;
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core_wr_row <= '0;
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core_wr_hash <= '0;
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end else begin
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core_wr_valid <= pending_q;
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core_wr_row <= row_q;
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if (WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)) begin
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core_wr_hash <= hash_q ^ flip_mask;
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end else begin
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core_wr_hash <= hash_q;
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end
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pending_q <= wr_valid && wr_ready;
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if (wr_valid && wr_ready) begin
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row_q <= wr_row;
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hash_q <= wr_hash;
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end
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end
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end
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endmodule
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