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https://github.com/SikongJueluo/Mini-Nav.git
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- Add cam_core_banked.sv with 8-lane banked CAM core - Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection - Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG - Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection - Add popcount_pipeline.sv for pipelined popcount operations - Refactor test_cam_basic.py with parametrized DUT introspection helpers - Add Python ref_model match_top1_with_read_noise() for read noise verification - Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups - Add new testbenches: test_cam_core_banked, test_cam_read_noise, test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8
55 lines
1.8 KiB
Systemverilog
55 lines
1.8 KiB
Systemverilog
//==============================================================================
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// CAM Parameter Definitions
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//==============================================================================
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// This file defines shared compile-time parameters for the Content-Addressable
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// Memory (CAM) subsystem. All `define macros use `ifndef guards to allow
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// command-line override via +define+.
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//
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// Macros:
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// NUM_ROWS — Number of rows in the CAM array
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// HASH_BITS — Width of the hash value in bits
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// LANES — Number of parallel comparison lanes
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// ROW_BITS — Bits needed to index NUM_ROWS rows ($clog2(NUM_ROWS))
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// SCORE_BITS — Bits needed to represent HASH_BITS-bit scores ($clog2(HASH_BITS+1))
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//
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// The TIE_BREAK_SENTINEL localparam is a bitmask with all bits set to 1'b1,
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// used as the initial / tie-breaking value in the row-priority arbiter.
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//==============================================================================
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`ifndef CAM_PARAMS_SVH
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`define CAM_PARAMS_SVH
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// Number of CAM rows.
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`ifndef NUM_ROWS
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`define NUM_ROWS 4096
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`endif
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// Width of the hash value stored per row.
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`ifndef HASH_BITS
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`define HASH_BITS 512
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`endif
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// Number of parallel comparison lanes.
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`ifndef LANES
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`define LANES 8
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`endif
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// Bits required to represent a row index.
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`ifndef ROW_BITS
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`define ROW_BITS $clog2(`NUM_ROWS)
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`endif
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// Bits required to represent a full-score count.
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`ifndef SCORE_BITS
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`define SCORE_BITS $clog2(`HASH_BITS + 1)
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`endif
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// Tie-break sentinel: all ones in the row-index width.
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// Used as the initial best-index value before any match is found.
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localparam logic [(`ROW_BITS)-1:0] TIE_BREAK_SENTINEL = {(`ROW_BITS){1'b1}};
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// First banked-pipeline implementation requires NUM_ROWS divisible by LANES.
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// Tail lanes and unaligned read batches are intentionally out of scope.
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`endif // CAM_PARAMS_SVH
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