85 lines
2.0 KiB
Verilog
85 lines
2.0 KiB
Verilog
module crop #(
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parameter IN_WIDTH = 1936 - 2,
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parameter IN_HEIGHT = 1088 - 2,
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parameter OFFSET_X = 8,
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parameter OFFSET_Y = 4,
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parameter OUT_WIDTH = 640,
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parameter OUT_HEIGHT = 480
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parameter COLOR_DEPTH = 8;
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) (
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input clk,
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input reset,
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input in_en,
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output reg in_que,
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input [3 * COLOR_DEPTH - 1:0] data_in,
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output reg out_en,
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input out_que,
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output reg [3 * COLOR_DEPTH - 1:0] data_out
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);
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wire fifo_en;
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wire fifo_full, fifo_empty;
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reg [11:0] cnt_x, cnt_y;
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async_fifo #(
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.DSIZE(3 * COLOR_DEPTH),
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.ASIZE(128)
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) fifo_image (
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.wclk(clk),
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.wrst_n(reset),
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.rclk(clk),
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.rrst_n(reset),
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.winc(fifo_en),
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.wdata(data_in),
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.wfull(fifo_full),
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.rinc(out_en),
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.rdata(data_out),
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.rempty(fifo_empty)
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);
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assign in_que = !fifo_full;
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assign out_en = (out_que && !fifo_empty) ? 1 : 0;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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in_que <= 0;
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out_en <= 0;
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data_out <= 0;
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cnt_x <= 0;
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cnt_y <= 0;
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end
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else begin
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if (in_en) begin
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if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
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if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
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fifo_en <= 1;
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end
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else begin
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fifo_en <= 0;
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end
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end
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else begin
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fifo_en <= 0;
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end
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cnt_x <= cnt_x + 1;
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if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
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cnt_x <= 0;
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if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
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cnt_y <= 0;
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end
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else begin
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cnt_y <= cnt_y + 1;
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end
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end
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end
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end
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end
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endmodule |