ISP/isp.v

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Verilog
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`timescale 1ns / 1ps
module isp #(
parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088,
parameter reg [15:0] OUT_WIDTH = 1920,
parameter reg [15:0] OUT_HEIGHT = 1080,
parameter reg [ 4:0] COLOR_DEPTH = 8,
parameter reg [ 1:0] RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
) (
// 基本信号
input wire clk,
input wire reset,
// 数据输入信号
input wire in_en,
input wire [15:0] in_data[3], // 数据输入线0、1、2分别表示第一、二、三行
output wire out_ready, // 数据请求线,高电平:请求三个数据,直到读取完才拉低
output wire out_receive,
output wire out_clk,
output wire out_en,
output wire [3 * COLOR_DEPTH - 1:0] out_data,
input wire in_ready,
input wire in_receive,
// 是否启动颜色矫正
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire color_correction
);
localparam reg [15:0] BAYER_WIDTH = IN_WIDTH - 2;
localparam reg [15:0] BAYER_HEIGHT = IN_HEIGHT - 2;
// 三通道合成RGB图像
wire blender_en, blender_ready, blender_receive;
wire [15:0] blender_r, blender_g, blender_b;
// 任意比例缩放图像
wire crop_en, crop_ready, crop_receive; // scaler 请求数据
reg [3 * COLOR_DEPTH - 1:0] crop_data;
// 写入RAM
// wire RAM_in_en;
// wire RAM_in_que; // RAM 请求数据
// wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
assign out_clk = clk;
Demosaic2 #(
.IM_WIDTH (IN_WIDTH),
.IM_HEIGHT(IN_HEIGHT),
.RAW_TYPE (RAW_TYPE)
) CFA (
.clk(clk),
.reset(reset),
.in_en(in_en),
.in_data(in_data),
.out_ready(out_ready),
.out_receive(out_receive),
.out_en(blender_en),
.in_ready(blender_ready),
.in_receive(blender_receive),
.out_r(blender_r),
.out_g(blender_g),
.out_b(blender_b)
);
ColorBlender #(
.IN_DEPTH (12),
.OUT_DEPTH(8)
) blender (
.clk (clk),
.reset(reset),
.in_en(blender_en),
.in_data({blender_r, blender_g, blender_b}),
.out_ready(blender_ready),
.out_receive(blender_receive),
.in_ready(crop_ready),
.in_receive(crop_receive),
.out_en(crop_en),
.out_data(crop_data),
.gain_red(gain_red),
.gain_green(gain_green),
.gain_blue(gain_blue),
.color_correction(color_correction)
);
Crop #(
.IN_WIDTH(BAYER_WIDTH),
.IN_HEIGHT(BAYER_HEIGHT),
.OUT_WIDTH(OUT_WIDTH),
.OUT_HEIGHT(OUT_HEIGHT),
.COLOR_DEPTH(COLOR_DEPTH)
) crop_process (
.clk (clk),
.reset(reset),
.in_en(crop_en),
.out_ready(crop_ready),
.out_receive(crop_receive),
.in_data(crop_data),
.out_en(out_en),
.in_ready(in_ready),
.in_receive(in_receive),
.out_data(out_data)
);
// RGB_to_RAM write_to_RAM (
// .clk(clk),
// .reset(reset),
// .in_en(RAM_in_en),
// .in_que(RAM_in_que),
// .in_data(RAM_in_data),
// .write_que(out_que),
// .write_en(out_en),
// .data_write(out_data)
// );
endmodule