170 lines
3.6 KiB
Verilog
170 lines
3.6 KiB
Verilog
`timescale 1ns/10ps
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`define End_CYCLE 100000000
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`define cycle 40.0
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`define PAT "./test.dat"
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`define OUT_F "./test.raw"
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module tb_demosaic();
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parameter WIDTH = 512;
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parameter HEIGHT = 256;
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parameter IMG_SIZE = WIDTH * HEIGHT;
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integer out_f, i, in_count, cycle_count;
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reg clk;
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reg reset;
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reg in_en;
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reg flag;
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wire wr_r, wr_g, wr_b;
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wire done;
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wire [13:0] addr_r, addr_g, addr_b;
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wire [7:0] wdata_r, wdata_g, wdata_b;
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reg [7:0] pixel, rdata_r, rdata_g, rdata_b;
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reg [7:0] PAT [0:IMG_SIZE-1];
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reg [7:0] MEM_R [0:IMG_SIZE-1];
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reg [7:0] MEM_G [0:IMG_SIZE-1];
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reg [7:0] MEM_B [0:IMG_SIZE-1];
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demosaic #(
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WIDTH,
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HEIGHT
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) u_demosaic (
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.clk(clk),
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.reset(reset),
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.in_en(in_en),
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.data_in(pixel),
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.wr_r(wr_r),
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.addr_r(addr_r),
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.wdata_r(wdata_r),
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.rdata_r(rdata_r),
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.wr_g(wr_g),
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.addr_g(addr_g),
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.wdata_g(wdata_g),
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.rdata_g(rdata_g),
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.wr_b(wr_b),
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.addr_b(addr_b),
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.wdata_b(wdata_b),
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.rdata_b(rdata_b),
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.done(done)
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);
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initial begin
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out_f = $fopen(`OUT_F, "wb");
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end
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initial begin
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$readmemh(`PAT, PAT);
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end
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initial begin
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clk = 0;
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reset = 0;
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in_en = 0;
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in_count = 0;
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cycle_count = 0;
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pixel = 'hx;
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rdata_r = 'hx;
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rdata_g = 'hx;
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rdata_b = 'hx;
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flag = 0;
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for(i = 0; i < IMG_SIZE; i = i + 1) begin
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MEM_R[i] = 0;
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MEM_G[i] = 0;
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MEM_B[i] = 0;
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end
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end
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always #(`cycle/2) clk = ~clk;
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initial begin
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$display("********************************************************************");
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$display("** Simulation Start **");
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$display("********************************************************************");
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@(posedge clk); #2 reset = 1'b1;
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#(`cycle*2);
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@(posedge clk); #2 reset = 1'b0;
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end
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initial begin
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@(posedge clk);
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# (`cycle*3) flag = 1;
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end
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always @ (negedge clk or posedge reset) begin // send mosaic image
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if(reset) begin
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pixel <= 0;
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in_en <= 0;
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end
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else begin
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if(flag) begin
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if(in_count <= IMG_SIZE-1) begin
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in_en <= 1;
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in_count <= in_count + 1;
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pixel <= PAT[in_count];
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end
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else begin
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in_en <= 0;
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pixel <= 'hx;
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end
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end
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end
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end
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always @ (negedge clk) begin // read memory, send data to module
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if(!wr_r)
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rdata_r <= MEM_R[addr_r];
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else
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rdata_r <= 'hx;
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if(!wr_g)
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rdata_g <= MEM_G[addr_g];
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else
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rdata_g <= 'hx;
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if(!wr_b)
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rdata_b <= MEM_B[addr_b];
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else
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rdata_b <= 'hx;
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end
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always @ (negedge clk) begin // write memory, read data and save
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if(wr_r) begin
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MEM_R[addr_r] <= wdata_r;
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end
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if(wr_g) begin
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MEM_G[addr_g] <= wdata_g;
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end
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if(wr_b) begin
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MEM_B[addr_b] <= wdata_b;
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end
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end
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always @ (posedge clk) begin // count cycle
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cycle_count <= cycle_count + 1;
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if(cycle_count >= `End_CYCLE) begin
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$display("********************************************************************");
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$display("** Fail waiting done signal **");
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$display("** You can increase END_CYCLE by yourself **");
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$display("********************************************************************");
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$finish;
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end
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end
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always @ (posedge clk) begin // check result
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if(done) begin
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for(i = 0; i < IMG_SIZE; i = i + 1) begin
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$fwrite(out_f, "%c", MEM_R[i]);
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$fwrite(out_f, "%c", MEM_G[i]);
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$fwrite(out_f, "%c", MEM_B[i]);
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end
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$fclose(out_f);
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$display("********************************************************************");
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$display("** Simulation completed successfully! **");
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$display("********************************************************************");
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$finish;
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end
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end
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endmodule
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