111 lines
3.1 KiB
Systemverilog
111 lines
3.1 KiB
Systemverilog
`timescale 1ns / 1ps
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// 三通道图像合成一个RGB图像
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module ColorBlender #(
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parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
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parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
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) (
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input wire clk,
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input wire reset,
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input wire in_en,
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input wire [15:0] in_data[3], // 0:R 1:G 2:B
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output wire out_ready,
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output wire out_receive,
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// 输出相关
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input wire in_ready,
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input wire in_receive,
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output reg out_en,
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output reg [OUT_DEPTH - 1:0] out_data[3],
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// 颜色校正
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input wire [15:0] gain_red,
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input wire [15:0] gain_green,
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input wire [15:0] gain_blue,
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input wire enable
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);
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localparam reg [2:0] READ_DATA = 0;
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localparam reg [2:0] CALC_DATA = 1;
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localparam reg [2:0] SATI_DATA = 2;
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localparam reg [2:0] SEND_DATA = 3;
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reg [2:0] state, nextState;
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reg [32 - 1:0] data_cal[3]; // 用于保存运算结果，防止溢出
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always @(posedge clk) begin
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if (reset) begin
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state <= READ_DATA;
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end else begin
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state <= nextState;
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end
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end
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always @(*) begin
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case (state)
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READ_DATA: nextState = (in_en) ? CALC_DATA : READ_DATA;
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CALC_DATA: nextState = SATI_DATA;
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SATI_DATA: nextState = SEND_DATA;
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SEND_DATA: nextState = (in_receive) ? READ_DATA : SEND_DATA;
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default: nextState = READ_DATA;
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endcase
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end
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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always @(posedge clk) begin
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if (reset) begin
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// 初始化
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data_cal[0] <= 0;
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data_cal[1] <= 0;
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data_cal[2] <= 0;
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out_data[0] <= 0;
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out_data[1] <= 0;
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out_data[2] <= 0;
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out_en <= 0;
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end else begin
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case (state)
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READ_DATA: begin
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if (in_en) begin
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data_cal[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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data_cal[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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data_cal[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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end
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end
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CALC_DATA: begin
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if (enable) begin
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data_cal[0] <= (data_cal[0] * {16'b0, gain_red}) >> 16;
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data_cal[1] <= (data_cal[1] * {16'b0, gain_green}) >> 16;
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data_cal[2] <= (data_cal[2] * {16'b0, gain_blue}) >> 16;
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end else begin
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data_cal[0] <= data_cal[0] >> 8;
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data_cal[1] <= data_cal[1] >> 8;
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data_cal[2] <= data_cal[2] >> 8;
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end
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end
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SATI_DATA: begin
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data_cal[0] <= |data_cal[0][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[0];
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data_cal[1] <= |data_cal[1][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[1];
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data_cal[2] <= |data_cal[2][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[2];
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end
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SEND_DATA: begin
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if (in_ready && !in_receive) begin
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out_en <= 1;
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out_data[0] <= data_cal[0][OUT_DEPTH-1:0];
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out_data[1] <= data_cal[1][OUT_DEPTH-1:0];
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out_data[2] <= data_cal[2][OUT_DEPTH-1:0];
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end else out_en <= 0;
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end
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default: ;
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endcase
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end
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end
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endmodule
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