91 lines
2.0 KiB
Verilog
91 lines
2.0 KiB
Verilog
`timescale 1ns/1ps
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module RGB_to_RAM #(
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parameter COLOR_DEPTH = 8,
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parameter FIFO_SIZE = 128
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) (
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input clk,
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input reset,
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// 数据输入
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output reg in_que,
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input in_en,
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input [3 * COLOR_DEPTH - 1:0] data_in,
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// 写入SRAM
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input write_que,
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output write_en,
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output [15:0] data_write
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);
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// 状态机
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localparam READ_DATA = 0;
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localparam SEND_R = 1;
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localparam SEND_GB = 2;
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reg [2:0] state, nextState;
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reg [3 * COLOR_DEPTH - 1:0] data_cache;
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reg [15:0] fifo_data;
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wire fifo_full, fifo_empty;
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async_fifo #(
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.DSIZE(16),
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.ASIZE(FIFO_SIZE)
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) fifo_image (
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.wclk(clk),
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.wrst_n(reset),
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.rclk(clk),
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.rrst_n(reset),
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.winc(in_en),
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.wdata(fifo_data),
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.wfull(fifo_full),
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.awfull(),
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.rinc(write_en),
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.rdata(data_write),
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.rempty(fifo_empty),
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.arempty()
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);
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// 当有数据请求且FIFO不为空时，输出数据
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assign write_en = (write_que && !fifo_empty) ? 1 : 0;
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always @(posedge clk or posedge reset) begin
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if (reset)
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state <= READ_DATA;
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else
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state <= nextState;
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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fifo_data <= 0;
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data_cache <= 0;
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end
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else begin
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case (state)
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// 读取数据
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READ_DATA: begin
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in_que <= 1;
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if (in_en) begin
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data_cache <= data_in;
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nextState <= SEND_R;
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end
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end
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SEND_R: begin
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in_que <= 0;
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fifo_data <= {8'b0, data_cache[3 * COLOR_DEPTH - 1:16]};
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nextState <= SEND_GB;
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end
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SEND_GB: begin
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fifo_data <= data_cache[15:0];
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nextState <= READ_DATA;
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end
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endcase
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end
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end
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endmodule
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