66 lines
1.3 KiB
Verilog
66 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
|
|
`include "DiffWidthSyncFIFO.v"
|
|
`default_nettype none
|
|
|
|
module tb_DiffWidthSyncFIFO;
|
|
localparam reg [7:0] DATA_WIDTH = 8;
|
|
localparam reg [7:0] DATA_DEPTH = 12;
|
|
localparam reg [7:0] READ_DEPTH = 3;
|
|
localparam reg [7:0] WRITE_DEPTH = 4;
|
|
reg clk;
|
|
reg reset;
|
|
reg write_en;
|
|
reg [DATA_WIDTH * WRITE_DEPTH - 1 : 0] write_data;
|
|
|
|
wire read_en, write_ready, read_ready;
|
|
wire [DATA_WIDTH * READ_DEPTH - 1 : 0] read_data;
|
|
|
|
|
|
DiffWidthSyncFIFO #(
|
|
.DATA_WIDTH (DATA_WIDTH),
|
|
.DATA_DEPTH (DATA_DEPTH),
|
|
.READ_DEPTH (READ_DEPTH),
|
|
.WRITE_DEPTH(WRITE_DEPTH)
|
|
) inst_fifo (
|
|
.clk (clk),
|
|
.reset(reset),
|
|
|
|
.read_ready(read_ready),
|
|
.read_en(read_en),
|
|
.read_data(read_data),
|
|
|
|
.write_ready(write_ready),
|
|
.write_en(write_en),
|
|
.write_data(write_data)
|
|
);
|
|
|
|
localparam CLK_PERIOD = 10;
|
|
always #(CLK_PERIOD / 2) clk = ~clk;
|
|
|
|
initial begin
|
|
$dumpfile("tb_DiffWidthSyncFIFO.vcd");
|
|
$dumpvars(0, tb_DiffWidthSyncFIFO);
|
|
end
|
|
|
|
assign read_ready = read_en ? 0 : 1;
|
|
|
|
initial begin
|
|
clk = 0;
|
|
reset = 0;
|
|
write_en = 0;
|
|
write_data = 0;
|
|
end
|
|
|
|
integer i;
|
|
initial begin
|
|
for (i = 0; i < 10; i = i + 1) begin
|
|
|
|
end
|
|
|
|
$finish(10 * CLK_PERIOD);
|
|
end
|
|
|
|
|
|
endmodule
|
|
`default_nettype wire
|