74 lines
2.1 KiB
Verilog
74 lines
2.1 KiB
Verilog
`timescale 1ns/1ps
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// 三通道图像合成一个RGB图像
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module chanels_to_RGB #(
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parameter IN_DEPTH = 12, // 输入图像的色深
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parameter OUT_DEPTH = 8 // 输出图像的色深
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) (
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input clk,
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input reset,
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input in_en,
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input [15:0] data_in [2:0], // 0:R 1:G 2:B
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// 输出相关
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input data_que, // 数据请求
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output out_en,
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output [3 * OUT_DEPTH - 1:0] data_out
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);
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reg [31:0] data_cal [2:0]; // 用于保存运算结果，防止溢出
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reg fifo_en;
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reg [3 * OUT_DEPTH - 1:0] fifo_in; // 输入fifo中缓存
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wire fifo_empty;
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// wire fifo_alempty;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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// 初始化
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data_cal[0] <= 0;
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data_cal[1] <= 0;
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data_cal[2] <= 0;
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fifo_en <= 0;
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fifo_in <= 0;
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end
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else begin
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if (in_en) begin
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data_cal[0] <= data_in[0] * OUT_DEPTH / IN_DEPTH;
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data_cal[1] <= data_in[1] * OUT_DEPTH / IN_DEPTH;
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data_cal[2] <= data_in[2] * OUT_DEPTH / IN_DEPTH;
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fifo_in <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0],data_cal[2][OUT_DEPTH - 1:0]};
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// data_out <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0],data_cal[2][OUT_DEPTH - 1:0]};
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end
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fifo_en <= in_en;
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end
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end
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// 存在数据请求且FIFO不为空时，才发送数据
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assign out_en = (data_que && !fifo_empty) ? 1 : 0;
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async_fifo #(
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.DSIZE(3 * OUT_DEPTH),
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.ASIZE(128),
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) RGB_FIFO (
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.wclk(clk),
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.rclk(clk),
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.wrst_n(reset),
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.rrst_n(reset),
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.winc(fifo_en),
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.wdata(fifo_in),
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/* verilator lint_off PINCONNECTEMPTY */
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.wfull(),
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/* verilator lint_off PINCONNECTEMPTY */
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.awfull(),
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/* verilator lint_off PINCONNECTEMPTY */
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.arempty(),
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.rempty(fifo_empty),
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.rdata(data_out),
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.rinc(out_en)
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);
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endmodule
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