101 lines
3.4 KiB
Systemverilog
101 lines
3.4 KiB
Systemverilog
module Demosaic_Pipeline #(
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parameter WINDOW_LENGTH = 3,
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parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
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parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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)(
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input wire clk,
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input wire reset,
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input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
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input wire [7:0] in_user,
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output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b
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output wire [7:0] out_user,
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready
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);
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localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
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localparam PIPILINE = 2;
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reg [PIPILINE-1:0] pipeline_valid;
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reg [7:0] pipeline_user[PIPILINE];
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wire pipeline_running;
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assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_running;
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = pipeline_valid[PIPILINE-1];
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assign out_user = pipeline_user[PIPILINE-1];
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reg pos_x, pos_y;
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reg [DATA_WIDTH-1:0] red, blue, green;
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reg [DATA_WIDTH-1:0] red_cache[4], blue_cache[4], green_cache[4];
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reg [1:0] raw_type;
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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for(i=0;i<4;i=i+1) red_cache[i] <= 0;
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for(i=0;i<4;i=i+1) blue_cache[i] <= 0;
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for(i=0;i<4;i=i+1) green_cache[i] <= 0;
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pipeline_valid <= 0;
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{red, green, blue} <= 0;
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{out_data[2],out_data[1],out_data[0]} <= 0;
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for(i=0;i<PIPILINE;i=i+1) pipeline_user[i] <= 0;
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pos_x <= 0;
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pos_y <= 0;
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end else if(pipeline_running) begin
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pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
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if(in_valid) begin
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pipeline_user[0] <= in_user;
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pos_x <= (in_user[0])?(0):(~pos_x);
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pos_y <= (in_user[0])?((in_user[1])?(0):(~pos_y)):(pos_y);
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red_cache[0] <= (in_data[3] >> 1) + (in_data[5] >> 1);
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red_cache[1] <= (in_data[0] >> 2) + (in_data[2] >> 2) + (in_data[6] >> 2) + (in_data[8] >> 2);
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red_cache[2] <= in_data[4];
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red_cache[3] <= (in_data[1] >> 1) + (in_data[7] >> 1);
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green_cache[0] <= in_data[4];
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green_cache[1] <= (in_data[1] >> 2) + (in_data[3] >> 2) + (in_data[5] >> 2) + (in_data[7] >> 2);
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green_cache[2] <= (in_data[1] >> 2) + (in_data[3] >> 2) + (in_data[5] >> 2) + (in_data[7] >> 2);
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green_cache[3] <= in_data[4];
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blue_cache[0] <= (in_data[1] >> 1) + (in_data[7] >> 1);
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blue_cache[1] <= in_data[4];
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blue_cache[2] <= (in_data[0] >> 2) + (in_data[2] >> 2) + (in_data[6] >> 2) + (in_data[8] >> 2);
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blue_cache[3] <= (in_data[3] >> 1) + (in_data[5] >> 1);
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end
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if(pipeline_valid[0]) begin
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pipeline_user[1] <= pipeline_user[0];
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out_data[2] <= red_cache[raw_type];
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out_data[1] <= green_cache[raw_type];
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out_data[0] <= blue_cache[raw_type];
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end
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end
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end
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// 0:grg 1:rgr 2:bgb 3:gbg 036 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
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// bgb gbg grg rgr 147
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// grg rgr bgb gbg 258
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always @(*) begin
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case (RAW_TYPE)
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2'b00: raw_type = { pos_y, pos_x};
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2'b01: raw_type = { pos_y, ~pos_x};
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2'b10: raw_type = {~pos_y, pos_x};
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2'b11: raw_type = {~pos_y, ~pos_x};
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endcase
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end
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endmodule
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