finish SaturationCorrection and pass simulation

Color/SaturationCorrection.v

@@ -17,14 +17,15 @@ module SaturationCorrection #(
     input wire in_receive,
 
     input wire enable,
-    input wire [8:0] saturation_inc
+    input wire signed [31:0] saturation_inc
 );
   reg [2:0] state, nextState;
   localparam reg [2:0] READ_DATA = 0;
   localparam reg [2:0] CALC_DATA = 1;
   localparam reg [2:0] SEND_DATA = 2;
 
-  reg [15:0] data_cal[3];
+  reg signed [31:0] data_cal[3], data_cache[3];
+  wire signed [31:0] max, min, delta, value, light, saturation, alpha;
 
   always @(posedge clk or posedge reset) begin
     if (reset) state <= READ_DATA;
@@ -43,19 +44,21 @@ module SaturationCorrection #(
   assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
   assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
 
-  assign max = data_cal[0] > data_cal[1]?
-               (data_cal[0] > data_cal[2] ? data_cal[0] : data_cal[2]):
-               (data_cal[1] > data_cal[2] ? data_cal[1] : data_cal[2]);
-  assign min = data_cal[0] < data_cal[1]?
-               (data_cal[0] < data_cal[2] ? data_cal[0] : data_cal[2]):
-               (data_cal[1] < data_cal[2] ? data_cal[1] : data_cal[2]);
+  assign max = data_cache[0] > data_cache[1]?
+               (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
+               (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
+  assign min = data_cache[0] < data_cache[1]?
+               (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
+               (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
   assign delta = max - min;
   assign value = max + min;
-  assign light = value >> 1;
-  assign saturation = (delta << 8) / max;
-
-
-
+  assign light = value >>> 1;
+  // assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value);
+  assign saturation = (delta <<< 8) / max;
+  assign alpha = (saturation_inc[31] == 0)
+                  ? ((saturation_inc + saturation >= 256)
+                    ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
+                    : (saturation_inc);
 
   always @(posedge clk or posedge reset) begin
     if (reset) begin
@@ -67,24 +70,45 @@ module SaturationCorrection #(
       data_cal[0] <= 0;
       data_cal[1] <= 0;
       data_cal[2] <= 0;
+      data_cache[0] <= 0;
+      data_cache[1] <= 0;
+      data_cache[2] <= 0;
     end else begin
       case (state)
         READ_DATA: begin
           if (in_en) begin
-
+            data_cache[0] <= {24'b0, in_data[0]};
+            data_cache[1] <= {24'b0, in_data[1]};
+            data_cache[2] <= {24'b0, in_data[2]};
           end
         end
 
         CALC_DATA: begin
           if (enable) begin
-
+            if (saturation_inc[31] == 0) begin
+              data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha);
+              data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha);
+              data_cal[2] <= (data_cache[2] << 8) + ((data_cache[2] - light) * alpha);
+            end else begin
+              data_cal[0] <= (light << 8) + (data_cache[0] - light) * (256 + alpha);
+              data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha);
+              data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha);
+            end
           end
         end
 
         SEND_DATA: begin
           if (in_ready) begin
             out_en <= 1;
-
+            if (enable && delta != 0) begin
+              out_data[0] <= (data_cal[0] <= 65535) ? (data_cal[0] > 0 ? data_cal[0][15:8] : 0) : 255;
+              out_data[1] <= (data_cal[1] <= 65535) ? (data_cal[1] > 1 ? data_cal[1][15:8] : 1) : 255;
+              out_data[2] <= (data_cal[2] <= 65535) ? (data_cal[2] > 2 ? data_cal[2][15:8] : 2) : 255;
+            end else begin
+              out_data[0] <= data_cache[0][7:0];
+              out_data[1] <= data_cache[1][7:0];
+              out_data[2] <= data_cache[2][7:0];
+            end
           end else out_en <= 0;
         end
 

Color/WhiteBalance.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+
+// 三通道图像合成一个RGB图像
+module WhiteBalance #(
+    parameter reg [4:0] IN_DEPTH  = 12,  // 输入图像的色深
+    parameter reg [4:0] OUT_DEPTH = 8,   // 输出图像的色深
+    parameter reg [8:0] BUFF_SIZE = 32
+) (
+    input wire clk,
+    input wire reset,
+
+    input wire in_en,
+    input wire [15:0] in_data[3],  // 0:R 1:G 2:B
+    output wire out_ready,
+    output wire out_receive,
+
+    // 输出相关
+    input wire in_ready,
+    input wire in_receive,
+    output reg out_en,
+    output reg [OUT_DEPTH - 1:0] out_data[3]
+
+);
+  localparam reg [2:0] READ_DATA = 0;
+  localparam reg [2:0] CALC_DATA = 1;
+  localparam reg [2:0] SATI_DATA = 2;
+  localparam reg [2:0] SEND_DATA = 3;
+
+  reg [2:0] state, nextState;
+  reg [BUFF_SIZE - 1:0] data_cal[3];  // 用于保存运算结果，防止溢出
+
+  always @(posedge clk or posedge reset) begin
+    if (reset) begin
+      state <= READ_DATA;
+    end else begin
+      state <= nextState;
+    end
+  end
+
+  always @(*) begin
+    case (state)
+      READ_DATA: nextState = (in_en) ? CALC_DATA : READ_DATA;
+      CALC_DATA: nextState = SATI_DATA;
+      SATI_DATA: nextState = SEND_DATA;
+      SEND_DATA: nextState = (in_receive) ? READ_DATA : SEND_DATA;
+      default:   nextState = READ_DATA;
+    endcase
+  end
+
+  assign out_ready   = (!in_en && state == READ_DATA) ? 1 : 0;
+  assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
+
+  always @(posedge clk or posedge reset) begin
+    if (reset) begin
+      // 初始化
+      data_cal[0] <= 0;
+      data_cal[1] <= 0;
+      data_cal[2] <= 0;
+
+      out_data[0] <= 0;
+      out_data[1] <= 0;
+      out_data[2] <= 0;
+      out_en <= 0;
+    end else begin
+      case (state)
+        READ_DATA: begin
+          if (in_en) begin
+
+          end
+        end
+
+        CALC_DATA: begin
+          if (enable) begin
+
+          end
+        end
+
+        SATI_DATA: begin
+
+        end
+
+        SEND_DATA: begin
+          if (in_ready && !in_receive) begin
+            out_en <= 1;
+
+          end else out_en <= 0;
+        end
+
+        default: ;
+      endcase
+    end
+  end
+
+endmodule