update scaler and RAM

This commit is contained in:
SikongJueluo
2024-05-11 21:53:35 +08:00
parent f3f01c1c51
commit c96e9b57b2
20 changed files with 1393 additions and 72 deletions
+67
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`timescale 1ns/1ps
// RGB
module chanels_to_RGB #(
parameter IN_DEPTH = 12, //
parameter OUT_DEPTH = 8 //
) (
input clk,
input reset,
input in_en,
input [IN_DEPTH - 1:0] data_in [2:0], // 0:R 1:G 2:B
//
input data_que; //
output reg out_en,
output reg [3 * OUT_DEPTH - 1:0] data_out
);
reg [31:0] data_cal [2:0]; //
reg fifo_en;
wire [3 * OUT_DEPTH - 1:0] fifo_in; // fifo
wire fifo_empty;
// wire fifo_alempty;
always @(posedge clk or posedge reset) begin
if (reset) begin
//
out_en <= 0;
data_out <= 0;
end
else begin
if (in_en) begin
data_cal[0] <= data_in[0] * OUT_DEPTH / IN_DEPTH;
data_cal[1] <= data_in[1] * OUT_DEPTH / IN_DEPTH;
data_cal[2] <= data_in[2] * OUT_DEPTH / IN_DEPTH;
fifo_in <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0],data_cal[2][OUT_DEPTH - 1:0]};
// data_out <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0],data_cal[2][OUT_DEPTH - 1:0]};
end
fifo_en <= in_en;
end
end
// FIFO
assign out_en <= (data_que && !fifo_empty) ? 1 : 0;
async_fifo #(
.DSIZE(3 * OUT_DEPTH),
.ASIZE(128),
) RGB_FIFO (
.wclk(clk),
.rclk(clk),
.wrst_n(reset),
.rrst_n(reset),
.winc(fifo_en),
.wdata(fifo_in),
// .wfull(),
// .awfull(),
// .arempty(fifo_alempty)
.rempty(fifo_empty),
.rdata(data_out),
.rinc(out_en)
);
endmodule