update scaler and RAM
This commit is contained in:
SikongJueluo
259
Demosaic/demosaic.v
Normal file
259
Demosaic/demosaic.v
Normal file
@@ -0,0 +1,259 @@
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module demosaic #(
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parameter IM_WIDTH = 512,
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parameter IM_HEIGHT = 256
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)(
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input clk,
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input reset,
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input in_en,
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input [7:0] data_in,
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output reg wr_r,
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output reg [13:0] addr_r,
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output reg [7:0] wdata_r,
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input [7:0] rdata_r,
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output reg wr_g,
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output reg [13:0] addr_g,
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output reg [7:0] wdata_g,
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input [7:0] rdata_g,
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output reg wr_b,
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output reg [13:0] addr_b,
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output reg [7:0] wdata_b,
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input [7:0] rdata_b,
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output reg done
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);
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parameter IM_SIZE = IM_HEIGHT * IM_WIDTH;
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// Register
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reg [1:0] bilinearCase;
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reg [2:0] state, nextState;
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reg [3:0] counter9;
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reg [6:0] round;
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reg [11:0] caseCounter;
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reg [7:0] data [8:0];
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reg [7:0] red, blue, green;
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reg [14:0] counter, biCounter; // bicounter store the center address
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// State parameter
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localparam READDATA = 0; // Read data, then wirte to wdata
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localparam COLOR = 1; // Choose the case of color
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localparam STORE9 = 2; // Store 9 element to register data
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localparam BILINEAR = 3; // Bilinear Interpolation
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localparam WRITEDATA = 4; // Write data to memory
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localparam FINISH = 5; // Done
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// State control
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always @(posedge clk or posedge reset) begin
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if(reset)
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state <= READDATA;
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else
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state <= nextState;
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end
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//next state logic
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always @(*) begin
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case (state)
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READDATA: nextState = (counter == IM_SIZE)? COLOR : READDATA;
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COLOR: nextState = STORE9;
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STORE9: nextState = (counter9 == 4'd9)? BILINEAR : STORE9;
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BILINEAR: nextState = WRITEDATA;
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WRITEDATA: nextState = (biCounter == ( IM_SIZE - IM_WIDTH + 1 ))? FINISH : COLOR;
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FINISH: nextState = FINISH;
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default: nextState = READDATA;
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endcase
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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done <= 1'd0;
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wr_r <= 1'd0;
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wr_g <= 1'd0;
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wr_b <= 1'd0;
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bilinearCase <= 2'd0;
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counter9 <= 4'd0;
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caseCounter <= 7'd0;
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round <= 7'd0;
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red <= 9'd0;
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blue <= 9'd0;
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green <= 9'd0;
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addr_r <= 14'd0;
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addr_g <= 14'd0;
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addr_b <= 14'd0;
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biCounter <= 15'd129;
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counter <= 15'd0;
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end
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else begin
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case (state)
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READDATA: begin
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if(in_en) begin
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wr_r <= 1'd1;
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wr_g <= 1'd1;
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wr_b <= 1'd1;
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addr_r <= counter;
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addr_g <= counter;
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addr_b <= counter;
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wdata_r <= data_in;
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wdata_g <= data_in;
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wdata_b <= data_in;
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counter <= counter + 1;
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end
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end
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COLOR: begin
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wr_r <= 1'd0;
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wr_g <= 1'd0;
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wr_b <= 1'd0;
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if(!(round & 1)) begin // Even round, 0,2,4,6,8,...
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if(!(caseCounter & 1)) // Even case, 0,2,4,6,8,...
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bilinearCase <= 2'd0;
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else // Odd case, 1,3,5,7,9,...
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bilinearCase <= 2'd1;
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end
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else begin // Odd round, 1,3,5,7,9,...
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if(!(caseCounter & 1)) // Even case, 0,2,4,6,8,...
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bilinearCase <= 2'd2;
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else // Odd case, 1,3,5,7,9,...
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bilinearCase <= 2'd3;
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end
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caseCounter <= caseCounter + 7'd1;
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end
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STORE9: begin
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wr_r <= 1'd0;
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wr_g <= 1'd0;
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wr_b <= 1'd0;
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/*
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* I use R,G,B memory to store pattern data. when in case 0(the middle color is green), I will update the missing blue and red data to memory.
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* In next turn is case 1(the middle color is blue). It will use previous data, but the blue and red data are changed in previous turn. So the
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* previous green data is the origin data.
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*/
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if(counter9 > 4'd0) begin
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case (bilinearCase)
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0: begin
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case (counter9)
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2: data[counter9 - 1] <= rdata_r;
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4: data[counter9 - 1] <= rdata_b;
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default: data[counter9 - 1] <= rdata_g;
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endcase
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end
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1: begin
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case (counter9)
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1,3: data[counter9 - 1] <= rdata_r;
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2,4: data[counter9 - 1] <= rdata_g;
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default: data[counter9 - 1] <= rdata_b;
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endcase
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end
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2: begin
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case (counter9)
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1,3: data[counter9 - 1] <= rdata_b;
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2,4: data[counter9 - 1] <= rdata_g;
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default: data[counter9 - 1] <= rdata_r;
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endcase
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end
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3: begin
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case (counter9)
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2: data[counter9 - 1] <= rdata_b;
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4: data[counter9 - 1] <= rdata_r;
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default: data[counter9 - 1] <= rdata_g;
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endcase
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end
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endcase
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end
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counter9 <= counter9 + 4'd1;
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case (counter9) // For y axis (row)
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0,1,2: begin
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addr_g[13:7] <= biCounter[13:7] - 7'd1;
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addr_r[13:7] <= biCounter[13:7] - 7'd1;
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addr_b[13:7] <= biCounter[13:7] - 7'd1;
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end
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3,4,5: begin
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addr_g[13:7] <= biCounter[13:7];
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addr_r[13:7] <= biCounter[13:7];
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addr_b[13:7] <= biCounter[13:7];
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end
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6,7,8: begin
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addr_g[13:7] <= biCounter[13:7] + 7'd1;
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addr_r[13:7] <= biCounter[13:7] + 7'd1;
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addr_b[13:7] <= biCounter[13:7] + 7'd1;
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end
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endcase
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case (counter9) // For x axis (col)
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0,3,6: begin
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addr_g[6:0] <= biCounter[6:0] - 7'd1;
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addr_r[6:0] <= biCounter[6:0] - 7'd1;
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addr_b[6:0] <= biCounter[6:0] - 7'd1;
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end
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1,4,7: begin
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addr_g[6:0] <= biCounter[6:0];
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addr_r[6:0] <= biCounter[6:0];
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addr_b[6:0] <= biCounter[6:0];
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end
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2,5,8: begin
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addr_g[6:0] <= biCounter[6:0] + 7'd1;
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addr_r[6:0] <= biCounter[6:0] + 7'd1;
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addr_b[6:0] <= biCounter[6:0] + 7'd1;
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end
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endcase
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end
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BILINEAR: begin
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// data case 0 case 1 case 2 case 3
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// 0 1 2 G R G R G R B G B G B G
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// 3 4 5 B G B G B G G R G R G R
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// 6 7 8 G R G R G R B G B G B G
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case (bilinearCase)
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0: begin // Missing B, R on G
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red <= (data[1] + data[7]) / 2;
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blue <= (data[3] + data[5]) / 2;
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green <= data[4];
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end
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1: begin // Missing G, R on B
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green <= (data[1] + data[3] + data[5] + data[7]) / 4;
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red <= (data[0] + data[2] + data[6] + data[8]) / 4;
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blue <= data[4];
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end
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2: begin // Missing G, B on R
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green <= (data[1] + data[3] + data[5] + data[7]) / 4;
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blue <= (data[0] + data[2] + data[6] + data[8]) / 4;
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red <= data[4];
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end
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3: begin // Missing B, R on G
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blue <= (data[1] + data[7]) / 2;
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red <= (data[3] + data[5]) / 2;
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green <= data[4];
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end
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endcase
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end
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WRITEDATA: begin
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wr_r <= 1'd1;
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wr_g <= 1'd1;
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wr_b <= 1'd1;
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addr_r <= biCounter;
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addr_g <= biCounter;
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addr_b <= biCounter;
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wdata_r <= red;
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wdata_g <= green;
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wdata_b <= blue;
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if(caseCounter == ( IM_WIDTH - 2 )) begin // Finish one row, then initialize the caseCounter
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caseCounter <= 7'd0;
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round <= round + 7'd1;
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biCounter <= biCounter + 15'd3; // Skip the edge
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end
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else
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biCounter <= biCounter + 15'd1;
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end
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FINISH: begin
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done <= 1'd1;
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end
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endcase
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end
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end
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endmodule
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165
Demosaic/demosaic2.v
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165
Demosaic/demosaic2.v
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@@ -0,0 +1,165 @@
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module demosaic2 #(
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parameter IM_WIDTH = 512, // 图像宽度
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parameter IM_HEIGHT = 256, // 图像高度
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parameter RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
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parameter DATA_SIZE = 16,
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)(
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// 基本信号
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input clk,
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input reset,
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// 数据输入信号
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input data_en,
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input [DATA_SIZE - 1:0] data_in [2:0], // 数据输入线，0、1、2分别表示第一、二、三行
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output reg data_que, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
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output reg data_line, // 新一行请求数据线，高电平：请求九个数据，直到读取完才拉低
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// en: 输出数据有效信号，高电平有效
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output reg out_en,
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output reg [DATA_SIZE - 1:0] out_r,
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output reg [DATA_SIZE - 1:0] out_g,
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output reg [DATA_SIZE - 1:0] out_b
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);
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// 常量，包括状态机
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// localparam IM_SIZE = IM_HEIGHT * IM_WIDTH;
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localparam READ_DATA = 0;
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localparam COLOR_GEN = 1;
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localparam WRITE_DATA = 2;
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localparam SLIDE_WINDOW = 3;
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// 寄存器
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reg [2:0] state, nextState;
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reg [15:0] data_cache [2:0][2:0]; // 缓存颜色数据，行列3x3
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reg [11:0] pos_x, pos_y; // 滑动窗口左上角位置
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reg [1:0] cnt_data; // 记录输入数据数量，最大值256
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reg [1:0] raw_type;
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reg [15:0] red, blue, green;
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// 三段状态机实现，窗口滑动，颜色计算
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// 状态切换
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always @(posedge clk or posedge reset) begin
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if (reset)
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state <= READ_DATA;
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else
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state <= nextState;
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end
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// 下一状态更新
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always @(*) begin
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case (state)
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// 记录够3x3个数据后，进行rgb转换
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READ_DATA: nextState = (cnt_data >= 3) ? COLOR_GEN : READ_DATA;
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COLOR_GEN: nextState = WRITE_DATA;
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WRITE_DATA: nextState = SLIDE_WINDOW;
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SLIDE_WINDOW: nextState = READ_DATA;
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endcase
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end
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// 各状态执行的操作
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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// 外部输出初始化
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out_en <= 0;
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out_r <= 0;
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out_g <= 0;
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out_r <= 0;
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data_que <= 0;
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data_line <= 1;
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// 内部寄存器初始化
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pos_x <= 0;
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pos_y <= 0;
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cnt_data <= 0;
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raw_type <= RAW_TYPE;
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end
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else begin
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// 状态机执行
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case (state)
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// 读取数据
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READ_DATA: begin
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data_que <= 1;
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if (cnt_data < 2)
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data_line <= 1;
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if (data_en) begin
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data_cache[cnt_data][0] <= data_in[0];
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data_cache[cnt_data][1] <= data_in[1];
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data_cache[cnt_data][2] <= data_in[2];
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cnt_data <= cnt_data + 1;
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end
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end
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COLOR_GEN: begin
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// 取消数据请求
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data_que <= 0;
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data_line <= 0;
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// 生成rgb图像
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case (raw_type)
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0: begin // Missing B, R on G
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red <= (data_cache[0][1] + data_cache[2][1]) / 2;
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blue <= (data_cache[1][0] + data_cache[1][2]) / 2;
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green <= data_cache[1][1];
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end
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1: begin // Missing G, R on B
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green <= (data_cache[0][1] + data_cache[1][0] + data_cache[1][2] + data_cache[2][1]) / 4;
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red <= (data_cache[0][0] + data_cache[0][2] + data_cache[2][0] + data_cache[2][2]) / 4;
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blue <= data_cache[1][1];
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end
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2: begin // Missing G, B on R
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green <= (data_cache[0][1] + data_cache[1][0] + data_cache[1][2] + data_cache[2][1]) / 4;
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blue <= (data_cache[0][0] + data_cache[0][2] + data_cache[2][0] + data_cache[2][2]) / 4;
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red <= data_cache[1][1];
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end
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3: begin // Missing B, R on G
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blue <= (data_cache[0][1] + data_cache[2][1]) / 2;
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red <= (data_cache[1][0] + data_cache[1][2]) / 2;
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green <= data_cache[1][1];
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end
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endcase
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raw_type <= raw_type + 1;
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end
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WRITE_DATA: begin
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out_en <= 1;
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out_r <= red;
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out_b <= blue;
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out_g <= green;
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end
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SLIDE_WINDOW: begin
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// 恢复相关寄存器变量
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out_en <= 0;
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// 记录位置寄存器自增，并处理缓存数据
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pos_x <= pos_x + 1;
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if (pos_x >= IM_WIDTH - 2) begin
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cnt_data <= 0;
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pos_x <= 0;
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pos_y <= pos_y + 1;
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if (pos_y >= IM_HEIGHT - 2)
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pos_y <= 0;
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end
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else begin
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cnt_data <= 2;
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// 窗口右移
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data_cache[0][0] <= data_cache[0][1];
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data_cache[1][0] <= data_cache[1][1];
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data_cache[2][0] <= data_cache[2][1];
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data_cache[0][1] <= data_cache[0][2];
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data_cache[1][1] <= data_cache[1][2];
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data_cache[2][1] <= data_cache[2][2];
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end
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end
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endcase
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end
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end
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endmodule
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169
Demosaic/sim/tb_demosaic.v
Normal file
169
Demosaic/sim/tb_demosaic.v
Normal file
@@ -0,0 +1,169 @@
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`timescale 1ns/10ps
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`define End_CYCLE 100000000
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`define cycle 40.0
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`define PAT "./test.dat"
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`define OUT_F "./test.raw"
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module tb_demosaic();
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parameter WIDTH = 512;
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parameter HEIGHT = 256;
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parameter IMG_SIZE = WIDTH * HEIGHT;
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integer out_f, i, in_count, cycle_count;
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reg clk;
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reg reset;
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reg in_en;
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reg flag;
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wire wr_r, wr_g, wr_b;
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wire done;
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wire [13:0] addr_r, addr_g, addr_b;
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wire [7:0] wdata_r, wdata_g, wdata_b;
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reg [7:0] pixel, rdata_r, rdata_g, rdata_b;
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reg [7:0] PAT [0:IMG_SIZE-1];
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reg [7:0] MEM_R [0:IMG_SIZE-1];
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reg [7:0] MEM_G [0:IMG_SIZE-1];
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reg [7:0] MEM_B [0:IMG_SIZE-1];
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demosaic #(
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WIDTH,
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||||
HEIGHT
|
||||
) u_demosaic (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.in_en(in_en),
|
||||
.data_in(pixel),
|
||||
.wr_r(wr_r),
|
||||
.addr_r(addr_r),
|
||||
.wdata_r(wdata_r),
|
||||
.rdata_r(rdata_r),
|
||||
.wr_g(wr_g),
|
||||
.addr_g(addr_g),
|
||||
.wdata_g(wdata_g),
|
||||
.rdata_g(rdata_g),
|
||||
.wr_b(wr_b),
|
||||
.addr_b(addr_b),
|
||||
.wdata_b(wdata_b),
|
||||
.rdata_b(rdata_b),
|
||||
.done(done)
|
||||
);
|
||||
|
||||
initial begin
|
||||
out_f = $fopen(`OUT_F, "wb");
|
||||
end
|
||||
|
||||
initial begin
|
||||
$readmemh(`PAT, PAT);
|
||||
end
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
reset = 0;
|
||||
in_en = 0;
|
||||
in_count = 0;
|
||||
cycle_count = 0;
|
||||
pixel = 'hx;
|
||||
rdata_r = 'hx;
|
||||
rdata_g = 'hx;
|
||||
rdata_b = 'hx;
|
||||
flag = 0;
|
||||
for(i = 0; i < IMG_SIZE; i = i + 1) begin
|
||||
MEM_R[i] = 0;
|
||||
MEM_G[i] = 0;
|
||||
MEM_B[i] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
always #(`cycle/2) clk = ~clk;
|
||||
|
||||
initial begin
|
||||
$display("********************************************************************");
|
||||
$display("** Simulation Start **");
|
||||
$display("********************************************************************");
|
||||
@(posedge clk); #2 reset = 1'b1;
|
||||
#(`cycle*2);
|
||||
@(posedge clk); #2 reset = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
@(posedge clk);
|
||||
# (`cycle*3) flag = 1;
|
||||
end
|
||||
|
||||
always @ (negedge clk or posedge reset) begin // send mosaic image
|
||||
if(reset) begin
|
||||
pixel <= 0;
|
||||
in_en <= 0;
|
||||
end
|
||||
else begin
|
||||
if(flag) begin
|
||||
if(in_count <= IMG_SIZE-1) begin
|
||||
in_en <= 1;
|
||||
in_count <= in_count + 1;
|
||||
pixel <= PAT[in_count];
|
||||
end
|
||||
else begin
|
||||
in_en <= 0;
|
||||
pixel <= 'hx;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @ (negedge clk) begin // read memory, send data to module
|
||||
if(!wr_r)
|
||||
rdata_r <= MEM_R[addr_r];
|
||||
else
|
||||
rdata_r <= 'hx;
|
||||
if(!wr_g)
|
||||
rdata_g <= MEM_G[addr_g];
|
||||
else
|
||||
rdata_g <= 'hx;
|
||||
if(!wr_b)
|
||||
rdata_b <= MEM_B[addr_b];
|
||||
else
|
||||
rdata_b <= 'hx;
|
||||
end
|
||||
|
||||
always @ (negedge clk) begin // write memory, read data and save
|
||||
if(wr_r) begin
|
||||
MEM_R[addr_r] <= wdata_r;
|
||||
end
|
||||
if(wr_g) begin
|
||||
MEM_G[addr_g] <= wdata_g;
|
||||
end
|
||||
if(wr_b) begin
|
||||
MEM_B[addr_b] <= wdata_b;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin // count cycle
|
||||
cycle_count <= cycle_count + 1;
|
||||
if(cycle_count >= `End_CYCLE) begin
|
||||
$display("********************************************************************");
|
||||
$display("** Fail waiting done signal **");
|
||||
$display("** You can increase END_CYCLE by yourself **");
|
||||
$display("********************************************************************");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin // check result
|
||||
if(done) begin
|
||||
for(i = 0; i < IMG_SIZE; i = i + 1) begin
|
||||
$fwrite(out_f, "%c", MEM_R[i]);
|
||||
$fwrite(out_f, "%c", MEM_G[i]);
|
||||
$fwrite(out_f, "%c", MEM_B[i]);
|
||||
end
|
||||
$fclose(out_f);
|
||||
$display("********************************************************************");
|
||||
$display("** Simulation completed successfully! **");
|
||||
$display("********************************************************************");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
262144
Demosaic/sim/test.dat
Normal file
262144
Demosaic/sim/test.dat
Normal file
File diff suppressed because it is too large
Load Diff
0
Demosaic/sim/test.raw
Normal file
0
Demosaic/sim/test.raw
Normal file
BIN
Demosaic/sim/transform/im.tif
Normal file
BIN
Demosaic/sim/transform/im.tif
Normal file
Binary file not shown.
19
Demosaic/sim/transform/raw_cut.py
Normal file
19
Demosaic/sim/transform/raw_cut.py
Normal file
@@ -0,0 +1,19 @@
|
||||
import imageio
|
||||
import numpy as np
|
||||
|
||||
cut_width = 512
|
||||
cut_height = 256
|
||||
|
||||
if __name__ == '__main__':
|
||||
txt = open('./test.dat', 'w')
|
||||
image = imageio.imread_v2('./im.tif')
|
||||
print(image.shape)
|
||||
cut = image[0:cut_height, 0:cut_width]
|
||||
print(cut.shape)
|
||||
cut = np.array(cut, dtype=np.int16)
|
||||
|
||||
for data in list(cut.flatten()):
|
||||
txt.write('%02x\n%02x\n' % (data & 0x00ff, (data & 0xff00) >> 4))
|
||||
txt.close()
|
||||
|
||||
imageio.imsave('./test.tif', cut)
|
||||
10
Demosaic/sim/transform/raw_to_image.py
Normal file
10
Demosaic/sim/transform/raw_to_image.py
Normal file
@@ -0,0 +1,10 @@
|
||||
import imageio
|
||||
import numpy as np
|
||||
|
||||
im_width = 1936
|
||||
im_height = 1088
|
||||
|
||||
if __name__ == '__main__':
|
||||
raw = np.fromfile('./test.raw', dtype=np.int8)
|
||||
image = raw.reshape((im_height, im_width))
|
||||
imageio.imsave("./test.tif", image)
|
||||
262144
Demosaic/sim/transform/test.dat
Normal file
262144
Demosaic/sim/transform/test.dat
Normal file
File diff suppressed because it is too large
Load Diff
BIN
Demosaic/sim/transform/test.tif
Normal file
BIN
Demosaic/sim/transform/test.tif
Normal file
Binary file not shown.
Reference in New Issue
Block a user