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finish reconstruction and pass simulation

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SikongJueluo
2024-06-28 19:38:36 +08:00
parent 85910958f9
commit c527835ff6
7 changed files with 372 additions and 310 deletions
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95
Crop/Crop.v Normal file
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module Crop #(
parameter reg [15:0] IN_WIDTH = 1934,
parameter reg [15:0] IN_HEIGHT = 1086,
parameter reg [15:0] OFFSET_X = 8,
parameter reg [15:0] OFFSET_Y = 4,
parameter reg [15:0] OUT_WIDTH = 640,
parameter reg [15:0] OUT_HEIGHT = 480,
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_en,
output wire out_ready,
output wire out_receive,
input wire [3 * COLOR_DEPTH - 1:0] in_data,
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [3 * COLOR_DEPTH - 1:0] out_data
);
reg [1:0] state, nextState;
localparam reg [1:0] READ_DATA = 0;
localparam reg [1:0] HANDLE_DATA = 1;
localparam reg [1:0] SEND_DATA = 2;
reg [15:0] cnt_x, cnt_y;
reg [3 * COLOR_DEPTH - 1:0] data;
wire is_valid;
// 状态切换
always @(posedge clk or posedge reset) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
// 下一状态更新
always @(*) begin
case (state)
READ_DATA: nextState = in_en ? HANDLE_DATA : READ_DATA;
HANDLE_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = (is_valid && !in_receive) ? SEND_DATA : READ_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) &&
(OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
cnt_x <= 0;
cnt_y <= 0;
data <= 0;
out_en <= 0;
out_data <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data <= in_data;
end
end
HANDLE_DATA: begin
if (cnt_x >= IN_WIDTH - 1) begin
cnt_x <= 0;
cnt_y <= cnt_y + 1;
end else begin
cnt_x <= cnt_x + 1;
end
if (cnt_y >= IN_HEIGHT - 1) begin
cnt_y <= 0;
end
end
SEND_DATA: begin
if (in_ready && !in_receive && is_valid) begin
out_en <= 1;
out_data <= data;
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule

91
Crop/crop.v
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module crop #(
parameter IN_WIDTH = 1934,
parameter IN_HEIGHT = 1086,
parameter OFFSET_X = 8,
parameter OFFSET_Y = 4,
parameter OUT_WIDTH = 640,
parameter OUT_HEIGHT = 480,
parameter COLOR_DEPTH = 8
) (
input clk,
input reset,
input in_en,
output reg in_que,
input [3 * COLOR_DEPTH - 1:0] data_in,
output reg out_en,
output reg [3 * COLOR_DEPTH - 1:0] data_out
);
localparam READ_DATA = 0;
localparam HANDLE_DATA = 1;
localparam SEND_DATA = 2;
reg [1:0] state, nextState;
reg [31:0] cnt_x, cnt_y;
reg [3 * COLOR_DEPTH - 1:0] data;
// 状态切换
always @(posedge clk or posedge reset) begin
if (reset)
state <= READ_DATA;
else
state <= nextState;
end
// 下一状态更新
always @(*) begin
case (state)
READ_DATA: nextState = (in_que && in_en) ? HANDLE_DATA : READ_DATA;
HANDLE_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = READ_DATA;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
cnt_x <= 0;
cnt_y <= 0;
data <= 0;
end
else begin
case (state)
READ_DATA: begin
in_que <= 1;
if (in_en) begin
data <= data_in;
in_que <= 0;
end
end
HANDLE_DATA: begin
if (OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) begin
if (OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH)) begin
out_en <= 1;
end
end
if (cnt_x >= IN_WIDTH - 1) begin
cnt_x <= 0;
cnt_y <= cnt_y + 1;
end
else begin
cnt_x <= cnt_x + 1;
end
if (cnt_y >= IN_HEIGHT - 1) begin
cnt_y <= 0;
end
end
SEND_DATA: begin
data_out <= data;
out_en <= 0;
end
endcase
end
end
endmodule