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fix demosaic not work correctly and polish project manage

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SikongJueluo
2024-10-25 23:12:57 +08:00
parent 1ab1467569
commit a8fa609228
17 changed files with 493 additions and 140 deletions
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4
rtl/Color/ColorBlender_Pipeline.sv
View File

@@ -71,9 +71,9 @@ module ColorBlender_Pipeline #(
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_blue}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_red}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;

90
rtl/Color/GammaCorrection_Pipeline.sv
View File

@@ -1,84 +1,42 @@
`timescale 1ns / 1ps
module GammaCorrection_Pipeline #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
module GammaCorrection_Pipeline
import common::*;
#(
parameter bit [4:0] COLOR_DEPTH = 8
) (
input var clk,
input var reset,
input wire in_valid,
output reg out_valid,
input var in_ready,
input var in_valid,
input var [COLOR_DEPTH - 1 : 0] in_data[3],
input wire in_ready,
output wire out_ready,
output var out_ready,
output var out_valid,
output var [COLOR_DEPTH - 1 : 0] out_data[3],
input wire in_hsync,
output wire out_hsync,
output var out_hsync,
output var out_fsync,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
input var [7:0] in_Gtable[256],
input var in_enable
);
Color color;
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
assign out_ready = in_ready;
input wire [7:0] gamma_table[256],
input wire enable
);
reg [7:0] data_cache[3];
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk)
begin
if (reset)
begin
out_en <= 0;
always_ff @(posedge clock) begin : blockName
if (reset) begin
out_valid <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
end else begin
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
end
else
begin
case (state)
READ_DATA:
begin
if (in_en)
begin
data_cache[0] <= in_data[0];
data_cache[1] <= in_data[1];
data_cache[2] <= in_data[2];
end
end
SEND_DATA:
begin
if (in_ready && !in_receive)
begin
out_en <= 1;
if (enable)
begin
out_data[0] <= gamma_table[data_cache[0]];
out_data[1] <= gamma_table[data_cache[1]];
out_data[2] <= gamma_table[data_cache[2]];
end
else
begin
out_data[0] <= data_cache[0];
out_data[1] <= data_cache[1];
out_data[2] <= data_cache[2];
end
end
else
out_en <= 0;
end
default:
;
endcase
end
end