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fix some bugs and pass lint check

This commit is contained in:
SelfConfusion 2024-05-13 11:29:03 +08:00
parent d9d6f039d2
commit 6111180f7a
10 changed files with 253 additions and 32 deletions
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2
.gitignore vendored
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@ -4,4 +4,4 @@
*.wlf
*.mpf
*.mti
/obj_dir/
*/obj_dir/

6
Crop/crop.v
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@ -4,8 +4,8 @@ module crop #(
parameter OFFSET_X = 8,
parameter OFFSET_Y = 4,
parameter OUT_WIDTH = 640,
parameter OUT_HEIGHT = 480
parameter COLOR_DEPTH = 8;
parameter OUT_HEIGHT = 480,
parameter COLOR_DEPTH = 8
) (
input clk,
input reset,
@ -82,4 +82,4 @@ module crop #(
end
end
endmodule
endmodule

4
Demosaic/demosaic2.v
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@ -1,8 +1,8 @@
module demosaic2 #(
parameter IM_WIDTH = 512, // 图像宽度
parameter IM_HEIGHT = 256, // 图像高度
parameter RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
parameter DATA_SIZE = 16,
parameter RAW_TYPE = 3, // 0:grbg 1:rggb 2:bggr 3:gbrg
parameter DATA_SIZE = 16
)(
// 基本信号
input clk,

119
Demosaic/sim/Makefile Normal file
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@ -0,0 +1,119 @@
######################################################################
#
# DESCRIPTION: Verilator Example: Small Makefile
#
# This calls the object directory makefile. That allows the objects to
# be placed in the "current directory" which simplifies the Makefile.
#
# This file ONLY is placed under the Creative Commons Public Domain, for
# any use, without warranty, 2020 by Wilson Snyder.
# SPDX-License-Identifier: CC0-1.0
#
######################################################################
# Check for sanity to avoid later confusion
ifneq ($(words $(CURDIR)),1)
$(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
endif
######################################################################
# Set up variables
# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
# package install, and verilator is in your path. Otherwise find the
# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
ifeq ($(VERILATOR_ROOT),)
VERILATOR = verilator
VERILATOR_COVERAGE = verilator_coverage
else
export VERILATOR_ROOT
VERILATOR = $(VERILATOR_ROOT)/bin/verilator
VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
endif
VERILATOR_FLAGS =
# Generate SystemC in executable form
VERILATOR_FLAGS += -sc --exe
# Generate makefile dependencies (not shown as complicates the Makefile)
#VERILATOR_FLAGS += -MMD
# Optimize
# VERILATOR_FLAGS += -x-assign fast
# Warn abount lint issues; may not want this on less solid designs
VERILATOR_FLAGS += -Wall
# Make waveforms
VERILATOR_FLAGS += --trace
# Check SystemVerilog assertions
VERILATOR_FLAGS += --assert
# Generate coverage analysis
# VERILATOR_FLAGS += --coverage
# Run Verilator in debug mode
#VERILATOR_FLAGS += --debug
# Add this trace to get a backtrace in gdb
#VERILATOR_FLAGS += --gdbbt
# Specify top module
TOP_MODULE = demosaic2
VERILATOR_FLAGS += -top $(TOP_MODULE)
# Input files for Verilator
VERILATOR_INPUT = ../demosaic2.v sc_demosaic.cpp
# Check if SC exists via a verilator call (empty if not)
SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
######################################################################
ifneq ($(SYSTEMC_EXISTS),)
default: run
else
default: nosc
endif
run:
@echo
@echo "-- Verilator tracing example"
@echo
@echo "-- VERILATE ----------------"
$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
@echo
@echo "-- COMPILE -----------------"
# To compile, we can either
# 1. Pass --build to Verilator by editing VERILATOR_FLAGS above.
# 2. Or, run the make rules Verilator does:
# $(MAKE) -j -C obj_dir -f Vtop.mk
# 3. Or, call a submakefile where we can override the rules ourselves:
$(MAKE) -j -C obj_dir -f V$(TOP_MODULE).mk
@echo
@echo "-- RUN ---------------------"
@rm -rf logs
@mkdir -p logs
obj_dir/Vtop +trace
@echo
@echo "-- COVERAGE ----------------"
@rm -rf logs/annotated
$(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat
@echo
@echo "-- DONE --------------------"
@echo "To see waveforms, open vlt_dump.vcd in a waveform viewer"
@echo
######################################################################
# Other targets
nosc:
@echo
@echo "%Skip: SYSTEMC_INCLUDE not in environment"
@echo "(If you have SystemC see the README, and rebuild Verilator)"
@echo
show-config:
$(VERILATOR) -V
maintainer-copy::
clean mostlyclean distclean maintainer-clean::
-rm -rf obj_dir logs *.log *.dmp *.vpd coverage.dat core

110
Demosaic/sim/sc_demosaic.cpp Normal file
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@ -0,0 +1,110 @@
// For std::unique_ptr
#include <memory>
// SystemC global header
#include <systemc>
// Include common routines
#include <verilated.h>
#include <verilated_vcd_sc.h>
#include <sys/stat.h> // mkdir
// Include model header, generated from Verilating "top.v"
#include "Vdemosaic2.h"
using namespace sc_core;
using namespace sc_dt;
int sc_main(int argc, char* argv[]) {
// This is a more complicated example, please also see the simpler examples/make_hello_c.
// Create logs/ directory in case we have traces to put under it
Verilated::mkdir("logs");
// Set debug level, 0 is off, 9 is highest presently used
// May be overridden by commandArgs argument parsing
Verilated::debug(0);
// Randomization reset policy
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
// Before any evaluation, need to know to calculate those signals only used for tracing
Verilated::traceEverOn(true);
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
Verilated::commandArgs(argc, argv);
// General logfile
std::ios::sync_with_stdio();
// Define clocks
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
// Define interconnect
sc_signal<bool> reset;
sc_signal<uint32_t> in_small;
// Construct the Verilated model, from inside Vtop.h
// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end
const std::unique_ptr<Vdemosaic2> top{new Vdemosaic2{"top"}};
// Attach Vtop's signals to this upper model
top->clk(clk);
top->reset(reset);
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedVcdSc* tfp = nullptr;
const char* flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
tfp = new VerilatedVcdSc;
top->trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.vcd");
}
// Simulate until $finish
while (!Verilated::gotFinish()) {
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp) tfp->flush();
// Apply inputs
if (sc_time_stamp() > sc_time(1, SC_NS) && sc_time_stamp() < sc_time(10, SC_NS)) {
reset_l = !1; // Assert reset
} else {
reset_l = !0; // Deassert reset
}
// Simulate 1ns
sc_start(1, SC_NS);
}
// Final model cleanup
top->final();
// Close trace if opened
if (tfp) {
tfp->close();
tfp = nullptr;
}
// Coverage analysis (calling write only after the test is known to pass)
#if VM_COVERAGE
Verilated::mkdir("logs");
VerilatedCov::write("logs/coverage.dat");
#endif
// Return good completion status
return 0;
}

8
Makefile
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@ -50,9 +50,11 @@ VERILATOR_FLAGS += --assert
#VERILATOR_FLAGS += --debug
# Add this trace to get a backtrace in gdb
#VERILATOR_FLAGS += --gdbbt
# Specify top module
TOP_MODULE = isp
VERILATOR_FLAGS += -top $(TOP_MODULE)
# Input files for Verilator
VERILATOR_INPUT = -top isp isp.v sc_main.cpp ./CFA/demosaic2.v
VERILATOR_INPUT = isp.v sc_main.cpp ./Demosaic/demosaic2.v ./Crop/*.v ./FIFO/*.v ./Merge/*.v ./RAM/*.v
# Check if SC exists via a verilator call (empty if not)
SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
@ -80,7 +82,7 @@ run:
# 2. Or, run the make rules Verilator does:
# $(MAKE) -j -C obj_dir -f Vtop.mk
# 3. Or, call a submakefile where we can override the rules ourselves:
$(MAKE) -j -C obj_dir -f ../Makefile_obj
$(MAKE) -j -C obj_dir -f V$(TOP_MODULE).mk
@echo
@echo "-- RUN ---------------------"

6
Merge/chanels_to_RGB.v
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@ -12,7 +12,7 @@ module chanels_to_RGB #(
input [IN_DEPTH - 1:0] data_in [2:0], // 0:R 1:G 2:B
// 输出相关
input data_que; // 数据请求
input data_que, // 数据请求
output reg out_en,
output reg [3 * OUT_DEPTH - 1:0] data_out
);
@ -42,7 +42,7 @@ module chanels_to_RGB #(
end
// 存在数据请求且FIFO不为空时，才发送数据
assign out_en <= (data_que && !fifo_empty) ? 1 : 0;
assign out_en = (data_que && !fifo_empty) ? 1 : 0;
async_fifo #(
.DSIZE(3 * OUT_DEPTH),
@ -64,4 +64,4 @@ module chanels_to_RGB #(
.rinc(out_en)
);
endmodule
endmodule

5
RAM/RGB_to_RAM.v
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@ -59,7 +59,6 @@ module RGB_to_RAM #(
if (reset) begin
write_en <= 0;
data_write <= 0;
cnt <= 0;
fifo_data <= 0;
data_cache <= 0;
end
@ -76,7 +75,7 @@ module RGB_to_RAM #(
SEND_R: begin
in_que <= 0;
fifo_data <= {8'b0, data_cache[3 * COLOR_DEPTH - 1:16]}
fifo_data <= {8'b0, data_cache[3 * COLOR_DEPTH - 1:16]};
nextState <= SEND_GB;
end
@ -88,4 +87,4 @@ module RGB_to_RAM #(
end
end
endmodule
endmodule

15
isp.v
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@ -56,12 +56,13 @@ module isp #(
.clk(clk),
.reset(reset),
.in_en(rgb_en),
.data_in[0](im_red[11:0]),
.data_in[1](im_green[11:0]),
.data_in[2](im_red[11:0]),
.data_in({im_red[11:0], im_green[11:0], im_red[11:0]}),
// .data_in[0](im_red[11:0]),
// .data_in[1](im_green[11:0]),
// .data_in[2](im_red[11:0]),
.data_que(scale_que),
.out_en(scale_en),
.data_que(scale_in_que),
.out_en(scale_in_en),
.data_out(scale_in_data)
);
@ -82,8 +83,8 @@ module isp #(
.clk(clk),
.reset(reset),
.in_en(scale_en),
.in_que(scale_que),
.in_en(scale_in_en),
.in_que(scale_in_que),
.data_in(scale_in_data),
.write_que(out_que),

10
sc_main.cpp
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@ -6,9 +6,7 @@
// Include common routines
#include <verilated.h>
#if VM_TRACE
#include <verilated_vcd_sc.h>
#endif
#include <sys/stat.h> // mkdir
@ -32,10 +30,8 @@ int sc_main(int argc, char* argv[]) {
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
#if VM_TRACE
// Before any evaluation, need to know to calculate those signals only used for tracing
Verilated::traceEverOn(true);
#endif
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
@ -76,7 +72,6 @@ int sc_main(int argc, char* argv[]) {
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
#if VM_TRACE
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedVcdSc* tfp = nullptr;
@ -88,15 +83,12 @@ int sc_main(int argc, char* argv[]) {
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.vcd");
}
#endif
// Simulate until $finish
while (!Verilated::gotFinish()) {
#if VM_TRACE
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp) tfp->flush();
#endif
// Apply inputs
if (sc_time_stamp() > sc_time(1, SC_NS) && sc_time_stamp() < sc_time(10, SC_NS)) {
@ -113,12 +105,10 @@ int sc_main(int argc, char* argv[]) {
top->final();
// Close trace if opened
#if VM_TRACE
if (tfp) {
tfp->close();
tfp = nullptr;
}
#endif
// Coverage analysis (calling write only after the test is known to pass)
#if VM_COVERAGE