finish FIFO

RAM/DiffWidthSyncFIFO.v

@@ -11,56 +11,83 @@ module DiffWidthSyncFIFO #(
 
     input wire read_ready,
     output reg read_en,
-    output reg [DATA_WIDTH * READ_DEPTH - 1 : 0] read_data,
+    output reg [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH],
 
-    output reg write_ready,
+    output wire write_ready,
     input wire write_en,
-    input wire [DATA_WIDTH * WRITE_DEPTH - 1 : 0] write_data
+    input wire [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH]
 );
   reg [DATA_WIDTH - 1 : 0] data[DATA_DEPTH];
-  wire [7:0] occupancy;
+  reg [7:0] occupancy;
   reg [7:0] cnt_read, cnt_write;
   reg [7:0] wi, ri;
+  reg read_finish, write_finish;
 
-  assign occupancy = (cnt_write >= cnt_read)
-                     ? (cnt_write - cnt_read)
-                     : (cnt_write + DATA_DEPTH - cnt_read);
-
-  // write data to fifo
   always @(posedge clk or posedge reset) begin
     if (reset) begin
-      write_ready <= 0;
+      occupancy <= 0;
+    end
+    else begin
+      if (read_finish && write_finish) begin
+        occupancy <= occupancy + (WRITE_DEPTH - READ_DEPTH);
+      end
+      else if (read_finish) begin
+        occupancy <= occupancy - READ_DEPTH;
+      end
+      else if (write_finish) begin
+        occupancy <= occupancy + WRITE_DEPTH;
+      end
+      else begin
+        occupancy <= occupancy;
+      end
+    end
+  end
+
+  // write data to fifo
+  assign write_ready = ((DATA_DEPTH - occupancy) >= WRITE_DEPTH && !write_en) ? 1 : 0;
+  always @(posedge clk or posedge reset) begin
+    if (reset) begin
       cnt_write   <= 0;
+      wi <= 0;
+      write_finish <= 0;
     end else begin
-      if (write_en) begin
-        write_ready <= 0;
+      if (write_en && (DATA_DEPTH - occupancy) >= WRITE_DEPTH) begin
         for (wi = 0; wi < WRITE_DEPTH; wi = wi + 1) begin
-          data[cnt_write] <= write_data[DATA_WIDTH*(wi+1)-1 : wi*DATA_WIDTH];
+          data[cnt_write] <= write_data[wi];
 
           if (cnt_write < DATA_DEPTH - 1) cnt_write <= cnt_write + 1;
           else cnt_write <= 0;
         end
+        write_finish <= 1;
       end else begin
-        write_ready <= 1;
+        write_finish <= 0;
       end
     end
   end
 
+  integer i;
   always @(posedge clk or posedge reset) begin
     if (reset) begin
-      read_data <= 0;
+      for (i = 0; i < READ_DEPTH; i = i + 1) begin
+        read_data[i] <= 0;
+      end
+      ri <= 0;
+      read_en <= 0;
       cnt_read  <= 0;
+      read_finish <= 0;
     end else begin
-      if (read_ready) begin
+      if (read_ready && occupancy >= READ_DEPTH) begin
         read_en <= 1;
         for (ri = 0; ri < READ_DEPTH; ri = ri + 1) begin
-          read_data[DATA_WIDTH*(ri+1)-1:ri*DATA_WIDTH] <= data[cnt_read];
+          read_data[ri] <= data[cnt_read];
 
           if (cnt_read < DATA_DEPTH - 1) cnt_read <= cnt_read + 1;
           else cnt_read <= 0;
         end
+        read_finish <= 1;
       end else begin
         read_en <= 0;
+        read_finish <= 0;
       end
     end
   end

RAM/tb_DiffWidthSyncFIFO.v

@@ -10,10 +10,10 @@ module tb_DiffWidthSyncFIFO;
   reg clk;
   reg reset;
   reg write_en;
-  reg [DATA_WIDTH * WRITE_DEPTH - 1 : 0] write_data;
+  reg [DATA_WIDTH  - 1 : 0] write_data[WRITE_DEPTH];
 
   wire read_en, write_ready, read_ready;
-  wire [DATA_WIDTH * READ_DEPTH - 1 : 0] read_data;
+  wire [DATA_WIDTH  - 1 : 0] read_data[READ_DEPTH];
 
 
   DiffWidthSyncFIFO #(
@@ -44,20 +44,29 @@ module tb_DiffWidthSyncFIFO;
 
   assign read_ready = read_en ? 0 : 1;
 
+  integer j;
   initial begin
     clk = 0;
-    reset = 0;
+    reset = 1;
     write_en = 0;
-    write_data = 0;
+    for(j = 0; j < WRITE_DEPTH; j = j + 1)begin
+      write_data[j] = 0;
+    end
   end
 
   integer i;
   initial begin
-    for (i = 0; i < 10; i = i + 1) begin
-
+    #(10 * CLK_PERIOD) reset = 0;
+    for (i = 0; i < 20; i = i + 1) begin
+      #CLK_PERIOD
+      for (j = 0; j < WRITE_DEPTH; j = j + 1) begin
+        write_data[j] = {$mti_random} % (32'b1 << DATA_DEPTH);
+      end
+      write_en = 1;
+      #CLK_PERIOD write_en = 0;
     end
 
-    $finish(10 * CLK_PERIOD);
+    $finish(100 * CLK_PERIOD);
   end