SikongJueluo/ISP
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix DPC and reconstruct isp

Browse Source
This commit is contained in:
SikongJueluo
2024-11-03 20:38:29 +08:00
parent a8fa609228
commit 42f6cdbbda
41 changed files with 25742 additions and 693 deletions
Download Patch File Download Diff File Expand all files Collapse all files

98
src/modules_tb/example_tb.cpp Normal file
View File

@@ -0,0 +1,98 @@
// For read and write
#include <array>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <ios>
#include <iostream>
#include <vector>
// SystemC global header
#include "sysc/communication/sc_clock.h"
#include "sysc/communication/sc_signal.h"
#include "sysc/communication/sc_signal_ifs.h"
#include "sysc/kernel/sc_module.h"
#include <memory>
#include <systemc>
// Include common routines
#include "sysc/kernel/sc_time.h"
#include "verilated_fst_sc.h"
#include <sys/stat.h> // mkdir
#include <utility>
#include <verilated.h>
// Include model
#include "Vtb.h"
using namespace sc_core;
using namespace sc_dt;
int sc_main(int argc, char *argv[]) {
std::cout << "Enter into sc_main\n";
// Create logs/ directory in case we have traces to put under it
Verilated::mkdir("logs");
// Set debug level, 0 is off, 9 is highest presently used
// May be overridden by commandArgs argument parsing
Verilated::debug(0);
// Randomization reset policy
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
// Before any evaluation, need to know to calculate those signals only used
// for tracing
Verilated::traceEverOn(true);
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
Verilated::commandArgs(argc, argv);
// General logfile
std::ios::sync_with_stdio();
// Create model
Vtb tb("Vtb");
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedFstSc *tfp = nullptr;
const char *flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
tfp = new VerilatedFstSc;
tb.trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.fst");
}
while (!Verilated::gotFinish()) {
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp)
tfp->flush();
// Simulate 1ns
sc_start(1, SC_NS);
}
// Final model cleanup
tb.final();
// Close trace if opened
if (tfp) {
tfp->close();
tfp = nullptr;
}
// Return good completion status
return 0;
}

98
src/modules_tb/windows_tb.cpp Normal file
View File

@@ -0,0 +1,98 @@
// For read and write
#include <array>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <ios>
#include <iostream>
#include <vector>
// SystemC global header
#include "sysc/communication/sc_clock.h"
#include "sysc/communication/sc_signal.h"
#include "sysc/communication/sc_signal_ifs.h"
#include "sysc/kernel/sc_module.h"
#include <memory>
#include <systemc>
// Include common routines
#include "sysc/kernel/sc_time.h"
#include "verilated_fst_sc.h"
#include <sys/stat.h> // mkdir
#include <utility>
#include <verilated.h>
// Include model
#include "VWindows_tb.h"
using namespace sc_core;
using namespace sc_dt;
int sc_main(int argc, char *argv[]) {
std::cout << "Enter into sc_main\n";
// Create logs/ directory in case we have traces to put under it
Verilated::mkdir("logs");
// Set debug level, 0 is off, 9 is highest presently used
// May be overridden by commandArgs argument parsing
Verilated::debug(0);
// Randomization reset policy
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
// Before any evaluation, need to know to calculate those signals only used
// for tracing
Verilated::traceEverOn(true);
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
Verilated::commandArgs(argc, argv);
// Create model
VWindows_tb tb("VWindows_tb");
// General logfile
std::ios::sync_with_stdio();
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedFstSc *tfp = nullptr;
const char *flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/VWindows_tb.fst\n";
tfp = new VerilatedFstSc;
tb.trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/VWindows_tb.fst");
}
while (!Verilated::gotFinish()) {
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp)
tfp->flush();
// Simulate 1ns
sc_start(1, SC_NS);
}
// Final model cleanup
tb.final();
// Close trace if opened
if (tfp) {
tfp->close();
tfp = nullptr;
}
// Return good completion status
return 0;
}

86
src/sc_main_pipeline.cpp
View File

@@ -1,26 +1,27 @@
// For read and write
#include <array>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <ios>
#include <iostream>
#include <vector>
// SystemC global header
#include "spdlog/common.h"
#include "spdlog/logger.h"
#include "spdlog/sinks/basic_file_sink.h"
#include "sysc/communication/sc_clock.h"
#include "sysc/communication/sc_signal.h"
#include "sysc/communication/sc_signal_ifs.h"
#include "sysc/kernel/sc_module.h"
#include <memory>
#include <systemc>
// Include common routines
#include "sysc/kernel/sc_time.h"
#include "verilated_fst_sc.h"
#include <sys/stat.h> // mkdir
#include <utility>
#include <vector>
#include <verilated.h>
#include <verilated_vcd_sc.h>
// Include model header, generated from Verilating "isp.v"
#include "Visp_Pipeline.h"
@@ -29,17 +30,24 @@
#include "tb_isp.hpp"
// Spdlog library
#include "spdlog/common.h"
#include "spdlog/logger.h"
#include "spdlog/sinks/basic_file_sink.h"
#include "spdlog/sinks/stdout_color_sinks.h"
#include "spdlog/spdlog.h"
#include "verilated_vcd_sc.h"
// Image Parameters
static const uint16_t IMG_WIDTH = 1936;
static const uint16_t IMG_HEIGHT = 1088;
static const uint32_t IMG_SIZE = (IMG_WIDTH * IMG_HEIGHT);
static const uint16_t IN_WIDTH = 1936;
static const uint16_t IN_HEIGHT = 1088;
static const uint32_t IN_SIZE = (IN_WIDTH * IN_HEIGHT);
static const uint16_t OUT_WIDTH = 1920;
static const uint16_t OUT_HEIGHT = 1080;
static const uint32_t OUT_SIZE = (OUT_WIDTH * OUT_HEIGHT);
static const uint32_t FLAMES = 2;
static const uint32_t FLAMES = 3;
// Input image path and Output directory path
#ifndef INPUT_IMG
@@ -54,7 +62,7 @@ struct color_gain {
double red;
double green;
double blue;
} color_gain{2, 1, 1}, white_gain;
} color_gain{1, 1, 1}, white_gain;
static const double gamma_value = 2.2;
static const double sat_inc = 0.5;
@@ -72,10 +80,10 @@ int sc_main(int argc, char *argv[]) {
{std::make_shared<spdlog::sinks::stdout_color_sink_mt>(),
std::make_shared<spdlog::sinks::basic_file_sink_mt>(
fmt::format("{:s}/ISP.txt", OUTPUT_DIR), true)}));
// When Debug, set Debug level
#ifdef DEBUG
// When Debug, set Debug level
#ifdef DEBUG
logger->set_level(spdlog::level::debug);
#endif // DEBUG
#endif // DEBUG
spdlog::set_default_logger(logger);
spdlog::info("Succeefully init spdlog");
} catch (const spdlog::spdlog_ex &ex) {
@@ -95,13 +103,13 @@ int sc_main(int argc, char *argv[]) {
}
// Read and Transform Image
std::vector<uint16_t> in_image(IN_SIZE);
uint8_t *buf = new uint8_t[2 * IN_SIZE];
image.read((char *)buf, 2 * IN_SIZE);
std::array<uint16_t, IMG_SIZE> in_image;
uint8_t *buf = new uint8_t[2 * IMG_SIZE];
image.read((char *)buf, 2 * IMG_SIZE);
uint32_t i = 0;
for (int y = 0; y < IN_HEIGHT; y++) {
for (int x = 0; x < IN_WIDTH; x++) {
in_image[y * IN_WIDTH + x] =
for (int y = 0; y < IMG_HEIGHT; y++) {
for (int x = 0; x < IMG_WIDTH; x++) {
in_image[y * IMG_WIDTH + x] =
(uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
i += 2;
}
@@ -109,6 +117,10 @@ int sc_main(int argc, char *argv[]) {
// Close and delete image
image.close();
delete[] buf;
// Generate a block number
// std::array<uint16_t, IMG_SIZE> in_image;
// for(int i = 0; i < IMG_SIZE; ++i) in_image[i] = i;
spdlog::info("Finish Reading Image");
// This is a more complicated example, please also see the simpler
@@ -137,19 +149,23 @@ int sc_main(int argc, char *argv[]) {
std::ios::sync_with_stdio();
// Define clocks
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
sc_clock isp_clk{"isp_clk", 10, SC_NS, 0.5, 5, SC_NS, true};
sc_clock camer_clk{"camera_clk", 20, SC_NS, 0.5, 5, SC_NS, true};
// Define interconnect
sc_signal<bool> rst;
// ISP Modules in ports
sc_signal<bool> in_valid;
sc_signal<bool> in_ready;
sc_signal<uint32_t> in_data;
sc_signal<bool> in_hsync;
sc_signal<bool> in_fsync;
// ISP Modules out ports
sc_signal<bool> out_valid;
sc_signal<bool> out_ready;
sc_signal<uint32_t> out_data;
sc_signal<bool> out_hsync;
sc_signal<bool> out_fsync;
sc_signal<uint32_t> out_user;
sc_signal<bool> fifo_isp_adapter_h_pixel_correct;
sc_signal<bool> fifo_isp_adapter_v_pixel_correct;
// ISP Modules Enable Ports
sc_signal<bool> blender_enable;
sc_signal<bool> gamma_enable;
@@ -166,39 +182,51 @@ int sc_main(int argc, char *argv[]) {
// Construct the Verilated model, from inside Visp.h
Visp_Pipeline isp("Visp");
isp.clk(clk);
isp.isp_clk(isp_clk);
isp.camera_clk(camer_clk);
isp.reset(rst);
// Connect input signal
isp.in_valid(in_valid);
isp.in_ready(in_ready);
isp.in_data(in_data);
isp.in_hsync(in_hsync);
isp.in_fsync(in_fsync);
// Connect output signal
isp.out_valid(out_valid);
isp.out_ready(out_ready);
isp.out_data(out_data);
isp.hsync(out_hsync);
isp.fsync(out_fsync);
isp.out_user(out_user);
isp.fifo_isp_adapter_h_pixel_correct(fifo_isp_adapter_h_pixel_correct);
isp.fifo_isp_adapter_v_pixel_correct(fifo_isp_adapter_v_pixel_correct);
// ISP Settings
// Connect ISP modules enable signal
isp.blender_enable(blender_enable);
// isp.gamma_enable(gamma_enable);
// Connect ISP modules configuration signal
isp.gain_red(gain_red);
isp.gain_green(gain_green);
isp.gain_blue(gain_blue);
// for (int i = 0; i < 256; ++i)
// isp.Gtable[i](gamma_table[i]);
// Construct testbench module
TB_ISP tb_isp("tb_isp", IN_WIDTH, IN_HEIGHT, OUT_WIDTH, OUT_HEIGHT, FLAMES,
OUTPUT_DIR);
tb_isp.image = std::move(in_image);
tb_isp.clk(clk);
TB_ISP tb_isp("tb_isp", IMG_WIDTH, IMG_HEIGHT, IN_WIDTH, IN_HEIGHT, OUT_WIDTH,
OUT_HEIGHT, FLAMES, OUTPUT_DIR);
tb_isp.image = in_image.data();
tb_isp.write_clk(camer_clk);
tb_isp.read_clk(isp_clk);
tb_isp.rst(rst);
// Connect input signal
tb_isp.in_valid(out_valid);
tb_isp.in_ready(out_ready);
tb_isp.in_data(out_data);
tb_isp.in_user(out_user);
// Connect output signal
tb_isp.out_valid(in_valid);
tb_isp.out_ready(in_ready);
tb_isp.out_data(in_data);
tb_isp.out_hsync(in_hsync);
tb_isp.out_fsync(in_fsync);
// Set ISP modules parameters
// Color Blender
@@ -229,15 +257,15 @@ int sc_main(int argc, char *argv[]) {
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedVcdSc *tfp = nullptr;
VerilatedFstSc *tfp = nullptr;
const char *flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
spdlog::info("Enabling waves into logs/vlt_dump.vcd...");
tfp = new VerilatedVcdSc;
tfp = new VerilatedFstSc;
isp.trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.vcd");
tfp->open("logs/vlt_dump.fst");
}
// Simulate until $finish

129
src/tb_isp.hpp
View File

@@ -2,6 +2,7 @@
#define __TB_ISP_H__
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <memory>
#include <sys/types.h>
@@ -15,6 +16,8 @@
#include "spdlog/sinks/basic_file_sink.h"
#include "spdlog/sinks/stdout_color_sinks.h"
#include "spdlog/spdlog.h"
#include "sysc/communication/sc_clock_ports.h"
#include "sysc/communication/sc_signal_ports.h"
SC_MODULE(TB_ISP) {
@@ -23,7 +26,8 @@ private:
spdlog::logger img_log;
public:
sc_core::sc_in_clk clk;
sc_core::sc_in_clk read_clk;
sc_core::sc_in_clk write_clk;
sc_core::sc_in<bool> rst;
sc_core::sc_in<bool> in_ready; // next module ready to receive data
@@ -34,6 +38,14 @@ public:
sc_core::sc_out<bool> out_ready; // this module ready to receive data
sc_core::sc_in<uint32_t> in_data; // this module receive data
sc_core::sc_out<bool> out_hsync;
sc_core::sc_out<bool> out_fsync;
sc_core::sc_in<uint32_t> in_user;
const uint16_t IMG_WIDTH;
const uint16_t IMG_HEIGHT;
const uint32_t IMG_SIZE;
const uint16_t IN_WIDTH;
const uint16_t IN_HEIGHT;
const uint32_t IN_SIZE;
@@ -43,18 +55,20 @@ public:
const uint32_t FLAMES;
const std::string OUT_DIR;
bool is_done; // when receive all data
std::vector<uint16_t> image; // the data of image
std::vector<uint32_t> process_image; // after isp process, the data of image
bool is_done; // when receive all data
uint16_t *image; // the data of image
uint32_t *process_image; // image after process
SC_CTOR(TB_ISP, const uint16_t in_width, const uint16_t in_height,
SC_CTOR(TB_ISP, const uint16_t img_width, const uint16_t img_height,
const uint16_t in_width, const uint16_t in_height,
const uint16_t out_width, const uint16_t out_height,
const uint32_t cnt_flame, const std::string &out_dir)
// Init class varibles
: IN_WIDTH(in_width), IN_HEIGHT(in_height), IN_SIZE(in_width * in_height),
: IMG_WIDTH(img_width), IMG_HEIGHT(img_height),
IMG_SIZE(img_width * img_height), IN_WIDTH(in_width),
IN_HEIGHT(in_height), IN_SIZE(in_width * in_height),
OUT_WIDTH(out_width), OUT_HEIGHT(out_height),
OUT_SIZE(out_width * out_height), FLAMES(cnt_flame), OUT_DIR(out_dir),
process_image(std::vector<uint32_t>(out_width * out_height, 0)),
// Global logger with file and stdout
log("TB_ISP",
spdlog::sinks_init_list(
@@ -69,47 +83,66 @@ public:
log.set_level(spdlog::level::debug);
img_log.set_level(spdlog::level::debug);
#endif // DEBUG
process_image = new uint32_t[OUT_SIZE];
SC_CTHREAD(sendData, clk.pos()); // when clk posedge, exec sendData
reset_signal_is(rst, true); // set rst signal
SC_CTHREAD(sendData, write_clk.pos()); // when clk posedge, exec sendData
reset_signal_is(rst, true); // set rst signal
SC_CTHREAD(readData, clk.pos());
SC_CTHREAD(readData, read_clk.pos());
reset_signal_is(rst, true); // set rst signal
log.info("Created TB_ISP Modules");
}
~TB_ISP() { delete[] process_image; }
void sendData(void) {
// init var
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
bool is_finish = false; // when send all data
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0, data = 0;
// reset
out_valid = false;
out_fsync = false;
out_hsync = false;
out_data = 0;
// generate fsync
out_fsync = true;
for (int i = std::rand() % 10 + 1; i > 0; --i)
wait();
out_fsync = false;
while (true) {
if (in_ready && !is_finish) {
// valid and send data
out_valid = true;
out_data = image[(pos_y + 0) * IN_WIDTH + pos_x];
if (in_ready) {
// print data
log.debug("x={:4d}, y={:4d}, data=0x{:04x}", pos_x, pos_y,
image[pos_y * IN_WIDTH + pos_x]);
pos_x++;
if (pos_x < IN_WIDTH && pos_y < IN_HEIGHT) {
// calculate position and recognize when to finish
if (pos_x >= IN_WIDTH) {
// valid and send data
out_valid = true;
out_hsync = true;
data = image[(pos_y + 0) * IMG_WIDTH + pos_x];
out_data = data;
// print data
log.debug("flame={:2d}, x={:4d}, y={:4d}, data=0x{:04x}", cnt_flame,
pos_x, pos_y, data);
pos_x++;
} else {
pos_x = 0;
out_hsync = false;
out_valid = false;
pos_y++;
}
// calculate position and recognize when to finish
if (pos_y >= IN_HEIGHT) {
out_fsync = true;
for (int i = std::rand() % 10 + 1; i > 0; --i)
wait();
out_fsync = false;
pos_y = 0;
cnt_flame++;
}
if (cnt_flame >= FLAMES + 1) {
is_finish = true;
}
} else {
out_valid = false;
}
@@ -122,6 +155,7 @@ public:
void readData(void) {
// init local var
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
uint32_t location = 0;
uint32_t last_data = 0, cnt = 0;
bool is_finish = false;
// reset
@@ -132,25 +166,31 @@ public:
if (!is_finish) {
out_ready = true;
// when data valid, write it down
if (in_valid) {
process_image[pos_y * OUT_WIDTH + pos_x] = in_data;
// calculate position
pos_x++;
if (pos_x >= OUT_WIDTH) {
// when fsync valid, save img
if (in_user == 0x03) {
pos_x = 0;
pos_y++;
}
if (pos_y >= OUT_HEIGHT) {
pos_y = 0;
saveData(
("output_img_" + std::to_string(cnt_flame) + ".bmp").c_str());
cnt_flame++;
if (cnt_flame >= FLAMES) {
is_finish = true;
}
}
if (cnt_flame >= FLAMES) {
is_finish = true;
location = pos_y * OUT_WIDTH + pos_x;
process_image[location] = in_data;
img_log.info("Flame {:d}: Receive {:d} pixels\tWait {:d} pixels",
cnt_flame, location, OUT_SIZE - location);
// calculate position
pos_x++;
if (pos_x >= OUT_WIDTH) {
pos_x = 0;
pos_y++;
}
}
} else {
@@ -178,12 +218,6 @@ public:
bool saveData(const char *name) {
bool ret = true;
// Check Image Size
if (process_image.size() > OUT_SIZE) {
log.error("Image Over Size!!!\nImage Size:{:d}", process_image.size());
return false;
}
// Write BMP image
bitmap_image bmp(OUT_WIDTH, OUT_HEIGHT);
if (!bmp) {
@@ -191,15 +225,14 @@ public:
return false;
}
img_log.info("Image Receive: {:d} Pixels, {:d} Bytes", process_image.size(),
process_image.size() * 3);
unsigned char red = 0, green = 0, blue = 0;
uint32_t data = 0;
for (int y = 0; y < OUT_HEIGHT; y++) {
for (int x = 0; x < OUT_WIDTH; x++) {
red = (process_image[y * OUT_WIDTH + x] & 0x00ff0000) >> 16;
green = (process_image[y * OUT_WIDTH + x] & 0x0000ff00) >> 8;
blue = (process_image[y * OUT_WIDTH + x] & 0x000000ff) >> 0;
data = process_image[y * OUT_WIDTH + x];
red = (data & 0x00ff0000) >> 16;
green = (data & 0x0000ff00) >> 8;
blue = (data & 0x000000ff) >> 0;
img_log.debug(
"x={:4d}, y={:4d}, red=0x{:02x}, green=0x{:02x}, blue=0x{:02x}", x,
y, red, green, blue);