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fix DPC and reconstruct isp

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SikongJueluo
2024-11-03 20:38:29 +08:00
parent a8fa609228
commit 42f6cdbbda
41 changed files with 25742 additions and 693 deletions
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5
rtl/Color/ColorBlender.sv
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@@ -1,4 +1,3 @@
`timescale 1ns/1ps
// 三通道图像合成一个RGB图像
module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
@@ -76,9 +75,9 @@ module ColorBlender #(
CALC_DATA: begin
if (enable) begin
data_cal[0] <= (data_cal[0] * {16'b0, gain_red}) >> 16;
data_cal[0] <= (data_cal[0] * {16'b0, gain_blue}) >> 16;
data_cal[1] <= (data_cal[1] * {16'b0, gain_green}) >> 16;
data_cal[2] <= (data_cal[2] * {16'b0, gain_blue}) >> 16;
data_cal[2] <= (data_cal[2] * {16'b0, gain_red}) >> 16;
end else begin
data_cal[0] <= data_cal[0] >> 8;
data_cal[1] <= data_cal[1] >> 8;

64
rtl/Color/ColorBlender_Pipeline.sv
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@@ -1,37 +1,34 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module ColorBlender_Pipeline #(
parameter reg [4:0] DATA_WIDTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
) (
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire [DATA_WIDTH - 1:0] in_data[3],
input wire [7:0] in_user,
output reg [OUT_DEPTH - 1:0] out_data[3],
output wire [7:0] out_user,
input wire in_valid,
input wire in_valid,
output wire out_valid,
input wire in_ready,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
// 颜色校正
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire enable
);
localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
reg [7:0] pipeline_user[PIPELINE];
reg [PIPELINE-1:0] pipeline_valid;
wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
@@ -39,9 +36,7 @@ module ColorBlender_Pipeline #(
assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
assign out_user = pipeline_user[PIPELINE-1];
reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3];
@@ -49,31 +44,30 @@ module ColorBlender_Pipeline #(
integer i;
always @(posedge clk) begin
if(reset) begin
if (reset) begin
pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
end else if(pipeline_flag) begin
for (i = 0; i < 3; i = i + 1) data_cal0[i] <= 0;
for (i = 0; i < 3; i = i + 1) data_cal1[i] <= 0;
for (i = 0; i < 3; i = i + 1) data_cal2[i] <= 0;
for (i = 0; i < 3; i = i + 1) out_data[i] <= 0;
for (i = 0; i < PIPELINE; i = i + 1) pipeline_user[i] <= 0;
end else if (pipeline_flag) begin
/************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
if (in_valid) begin
pipeline_user[0] <= in_user;
data_cal0[0] <= (in_data[0]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[1] <= (in_data[1]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[2] <= (in_data[2]) << (8 - (DATA_WIDTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_blue}) >> 16;
if (pipeline_valid[0]) begin
pipeline_user[1] <= pipeline_user[0];
if (enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_red}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;
@@ -81,13 +75,15 @@ module ColorBlender_Pipeline #(
end
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
if (pipeline_valid[1]) begin
pipeline_user[2] <= pipeline_user[1];
data_cal2[0] <= (|data_cal1[0][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (|data_cal1[1][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (|data_cal1[2][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin
if (pipeline_valid[2]) begin
pipeline_user[3] <= pipeline_user[2];
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];

2
rtl/Color/GammaCorrection.sv
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@@ -1,5 +1,3 @@
`timescale 1ns / 1ps
module GammaCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8
) (

93
rtl/Color/GammaCorrection_Pipeline.sv
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@@ -1,42 +1,91 @@
`timescale 1ns / 1ps
`include "common"
`include "vector"
`include "color"
module GammaCorrection_Pipeline
import common::*;
#(
parameter bit [4:0] COLOR_DEPTH = 8
parameter uint COLOR_DEPTH = 8
) (
input var clk,
input var reset,
input var rst,
input var in_ready,
input var in_valid,
input var [COLOR_DEPTH - 1 : 0] in_data[3],
input var i_ready,
input var i_valid,
input var [COLOR_DEPTH - 1 : 0] i_data[3],
output var out_ready,
output var out_valid,
output var [COLOR_DEPTH - 1 : 0] out_data[3],
output var o_ready,
output var o_valid,
output var [COLOR_DEPTH - 1 : 0] o_data[3],
output var out_hsync,
output var out_fsync,
input var i_hsync,
input var i_fsync,
output var o_hsync,
output var o_fsync,
input var [7:0] in_Gtable[256],
input var in_enable
input var [COLOR_DEPTH - 1:0] i_Gtable[2 ** COLOR_DEPTH],
input var i_enable
);
Color color;
// pipeline level
localparam uint PIPELINELEVEL = 2;
assign out_ready = in_ready;
// Define Color
`Typedef_Color(color_t, 8) color_t;
`Typedef_Vector(Vector_Color, color_t, PIPELINELEVEL - 1, PIPELINELEVEL - 1) Vector_Color;
Vector_Color color;
// shift queue: horizon sync and flame sync
`Typedef_Vector(Vector_Sync, bit, PIPELINELEVEL - 1, PIPELINELEVEL - 1) Vector_Sync;
Vector_Sync hsync, fsync;
always_ff @(posedge clock) begin : blockName
if (reset) begin
out_valid <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
// Pipeline status
`Typedef_Vector(Vector_Pipe, bit, PIPELINELEVEL, PIPELINELEVEL) Vector_Pipe;
Vector_Pipe pipeline_status;
assign o_ready = i_ready;
// Pipeline in: Read data
always_ff @(posedge clk) begin : Pipeline_in
if (rst) begin
pipeline_status <= `Vector_Pipe::f_clearWith(0);
hsync <= `Vector_Sync::f_clearWith(0);
fsync <= `Vector_Sync::f_clearWith(0);
end else begin
end
// read sync edge signal and push front
hsync <= `Vector_Sync::f_pushFront(i_hsync, hsync);
fsync <= `Vector_Sync::f_pushFront(i_fsync, fsync);
// push front i_valid signal
pipeline_status <= `Vector_Pipe::f_pushFront(i_valid, pipeline_status);
// read color data
if (i_valid) begin
color <= `Vector_Color::f_pushFront(`color_t::f_fromRGB(i_data[2], i_data[1], i_data[0]), color);
end else begin
end
end
end
// Pipeline 2: Send data
always_ff @(posedge clk) begin : Pipeline_1
if (rst) begin
o_data <= {0, 0, 0};
o_hsync <= 0;
o_fsync <= 0;
end else begin
// send the last sync signal from queue
o_hsync <= `Vector_Sync::f_getBack(hsync);
o_fsync <= `Vector_Sync::f_getBack(fsync);
// read adjust data from gamma table
// {o_data[2], o_data[1], o_data[0]} <= {
// i_Gtable[color.red], i_Gtable[color.green], i_Gtable[color.blue]
// };
o_valid <= 1;
end
end

3
rtl/Color/GreyWorld.sv
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@@ -1,6 +1,3 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module GreyWorld #(
parameter reg [4:0] COLOR_DEPTH = 8,

2
rtl/Color/SaturationCorrection.sv
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@@ -1,5 +1,3 @@
`timescale 1ns / 1ps
module SaturationCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8
) (

2
rtl/Color/WhiteBalance.sv
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@@ -1,5 +1,3 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module WhiteBalance #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深