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use cmake to replace makefiel

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SikongJueluo
2024-10-03 15:13:24 +08:00
parent 7e12105a3d
commit 35e6ab1e85
24 changed files with 1887 additions and 882 deletions
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162
rtl/Color/ColorBlender.sv
View File

@@ -1,5 +1,4 @@
`timescale 1ns / 1ps
`timescale 1ns/1ps
// 三通道图像合成一个RGB图像
module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
@@ -7,21 +6,17 @@ module ColorBlender #(
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
input wire in_en,
input wire [15:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [OUT_DEPTH - 1:0] out_data[3],
// 颜色校正
input wire [15:0] gain_red,
@@ -29,70 +24,85 @@ module ColorBlender #(
input wire [15:0] gain_blue,
input wire enable
);
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SATI_DATA = 2;
localparam reg [2:0] SEND_DATA = 3;
localparam PIPELINE = 4;
reg [2:0] state, nextState;
reg [32 - 1:0] data_cal[3]; // 用于保存运算结果，防止溢出
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3];
reg [32 - 1:0] data_cal2[3];
integer i;
always @(posedge clk) begin
if(reset) begin
pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
end else if(pipeline_flag) begin
/************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;
data_cal1[2] <= data_cal0[2] >> 8;
if (reset) begin
state <= READ_DATA;
end else begin
state <= nextState;
end
end
always @(*) begin
case (state)
READ_DATA: nextState = (in_en) ? CALC_DATA : READ_DATA;
CALC_DATA: nextState = SATI_DATA;
SATI_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = (in_receive) ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk) begin
if (reset) begin
// 初始化
data_cal[0] <= 0;
data_cal[1] <= 0;
data_cal[2] <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
out_en <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data_cal[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
end
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
end
CALC_DATA: begin
if (enable) begin
data_cal[0] <= (data_cal[0] * {16'b0, gain_red}) >> 16;
data_cal[1] <= (data_cal[1] * {16'b0, gain_green}) >> 16;
data_cal[2] <= (data_cal[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal[0] <= data_cal[0] >> 8;
data_cal[1] <= data_cal[1] >> 8;
data_cal[2] <= data_cal[2] >> 8;
end
end
SATI_DATA: begin
data_cal[0] <= |data_cal[0][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[0];
data_cal[1] <= |data_cal[1][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[1];
data_cal[2] <= |data_cal[2][31 : OUT_DEPTH] ? {32{1'b1}} : data_cal[2];
end
SEND_DATA: begin
if (in_ready && !in_receive) begin
out_en <= 1;
out_data[0] <= data_cal[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal[2][OUT_DEPTH-1:0];
end else out_en <= 0;
end
default: ;
endcase
end
end

99
rtl/Color/ColorBlender_Pipeline.sv Normal file
View File

@@ -0,0 +1,99 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
// 颜色校正
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire enable
);
localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3];
reg [32 - 1:0] data_cal2[3];
integer i;
always @(posedge clk) begin
if(reset) begin
pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
end else if(pipeline_flag) begin
/************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;
data_cal1[2] <= data_cal0[2] >> 8;
end
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
end
end
end
endmodule