finish Grey World White Balance

Crop/Crop.sv

@@ -13,12 +13,12 @@ module Crop #(
     input wire in_en,
     output wire out_ready,
     output wire out_receive,
-    input wire [3 * COLOR_DEPTH - 1:0] in_data,
+    input wire [COLOR_DEPTH - 1:0] in_data[3],
 
     input wire in_ready,
     input wire in_receive,
     output reg out_en,
-    output reg [3 * COLOR_DEPTH - 1:0] out_data
+    output reg [COLOR_DEPTH - 1:0] out_data[3]
 );
   reg [1:0] state, nextState;
   localparam reg [1:0] READ_DATA = 0;
@@ -26,11 +26,11 @@ module Crop #(
   localparam reg [1:0] SEND_DATA = 2;
 
   reg [15:0] cnt_x, cnt_y;
-  reg [3 * COLOR_DEPTH - 1:0] data;
+  reg [COLOR_DEPTH - 1:0] data[3];
   wire is_valid;
 
   // 状态切换
-  always @(posedge clk or posedge reset) begin
+  always @(posedge clk) begin
     if (reset) state <= READ_DATA;
     else state <= nextState;
   end
@@ -50,19 +50,25 @@ module Crop #(
   assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) &&
                     (OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0;
 
-  always @(posedge clk or posedge reset) begin
+  always @(posedge clk) begin
     if (reset) begin
       cnt_x <= 0;
       cnt_y <= 0;
-      data  <= 0;
+      data[0] <= 0;
+      data[1] <= 0;
+      data[2] <= 0;
 
       out_en <= 0;
-      out_data <= 0;
+      out_data[0] <= 0;
+      out_data[1] <= 0;
+      out_data[2] <= 0;
     end else begin
       case (state)
         READ_DATA: begin
           if (in_en) begin
-            data <= in_data;
+            data[0] <= in_data[0];
+            data[1] <= in_data[1];
+            data[2] <= in_data[2];
           end
         end
 
@@ -82,7 +88,9 @@ module Crop #(
         SEND_DATA: begin
           if (in_ready && !in_receive && is_valid) begin
             out_en   <= 1;
-            out_data <= data;
+            out_data[0] <= data[0];
+            out_data[1] <= data[1];
+            out_data[2] <= data[2];
           end else out_en <= 0;
         end