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finish Grey World White Balance

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SikongJueluo
2024-07-03 21:50:29 +08:00
parent 649d34415f
commit 1154da3307
12 changed files with 526 additions and 239 deletions
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4
Color/ColorBlender.sv
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@@ -34,7 +34,7 @@ module ColorBlender #(
reg [2:0] state, nextState;
reg [BUFF_SIZE - 1:0] data_cal[3]; // 用于保存运算结果，防止溢出
always @(posedge clk or posedge reset) begin
always @(posedge clk) begin
if (reset) begin
state <= READ_DATA;
end else begin
@@ -55,7 +55,7 @@ module ColorBlender #(
assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
always @(posedge clk or posedge reset) begin
always @(posedge clk) begin
if (reset) begin
// 初始化
data_cal[0] <= 0;

4
Color/GammaCorrection2.sv
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@@ -25,7 +25,7 @@ module GammaCorrection2 #(
reg [7:0] data_cache[3];
always @(posedge clk or posedge reset) begin
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
@@ -41,7 +41,7 @@ module GammaCorrection2 #(
assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
always @(posedge clk or posedge reset) begin
always @(posedge clk) begin
if (reset) begin
out_en <= 0;
out_data[0] <= 0;

134
Color/GreyWorld.sv Normal file
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@@ -0,0 +1,134 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module GreyWorld #(
parameter reg [4:0] COLOR_DEPTH = 8,
parameter reg [31:0] IM_SIZE = 1920 * 1080
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [7:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [COLOR_DEPTH - 1:0] out_data[3],
// Gain: red = 0.803881, green = 0.885894, blue = 1.594308
input wire enable,
input wire [8:0] flame_rate,
input wire [31:0] white_gain[3]
);
reg [2:0] state, nextState;
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SEND_DATA = 2;
reg [8:0] cnt_flame;
reg [31:0] red_total, green_total, blue_total, r_white_gain[3];
reg [31:0] data_cal[3], data_cache[3];
reg [31:0] cnt_pexels;
wire [31:0] average;
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
always @(*) begin
case (state)
READ_DATA: nextState = in_en ? CALC_DATA : READ_DATA;
CALC_DATA: nextState = SEND_DATA;
SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && !reset) ? 1 : 0;
assign out_receive = (in_en && !reset) ? 1 : 0;
assign average = ((red_total + green_total + blue_total) << 8) / (3 * IM_SIZE);
always @(posedge clk) begin
if (reset) begin
red_total <= 0;
green_total <= 0;
blue_total <= 0;
cnt_flame <= flame_rate;
cnt_pexels <= 0;
r_white_gain[0] <= white_gain[0];
r_white_gain[1] <= white_gain[1];
r_white_gain[2] <= white_gain[2];
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data_cache[0] <= {24'b0, in_data[0]};
data_cache[1] <= {24'b0, in_data[1]};
data_cache[2] <= {24'b0, in_data[2]};
if (cnt_flame == flame_rate) begin
red_total <= red_total + {24'b0, in_data[0]};
green_total <= green_total + {24'b0, in_data[0]};
blue_total <= blue_total + {24'b0, in_data[0]};
end
if (cnt_pexels < IM_SIZE) begin
cnt_pexels <= cnt_pexels + 1;
end else begin
cnt_pexels <= 0;
if (cnt_flame < flame_rate) cnt_flame <= cnt_flame + 1;
else cnt_flame <= 0;
end
end
end
CALC_DATA: begin
if (cnt_pexels >= IM_SIZE && cnt_flame == flame_rate) begin
r_white_gain[0] <= (average * ( IM_SIZE << 8 )) / red_total;
r_white_gain[1] <= (average * ( IM_SIZE << 8)) / green_total;
r_white_gain[2] <= (average * ( IM_SIZE << 8)) / blue_total;
end
data_cal[0] <= (data_cache[0] * r_white_gain[0]);
data_cal[1] <= (data_cache[1] * r_white_gain[1]);
data_cal[2] <= (data_cache[2] * r_white_gain[2]);
end
SEND_DATA: begin
if (in_ready) begin
out_en <= 1;
if (enable) begin
out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
out_data[1] <= (|data_cal[1][31:16]) ? 255 : (data_cal[1] > 0 ? data_cal[1][15:8] : 0);
out_data[2] <= (|data_cal[2][31:16]) ? 255 : (data_cal[2] > 0 ? data_cal[2][15:8] : 0);
end else begin
out_data[0] <= data_cache[0][7:0];
out_data[1] <= data_cache[1][7:0];
out_data[2] <= data_cache[2][7:0];
end
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule

10
Color/SaturationCorrection.sv
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@@ -27,7 +27,7 @@ module SaturationCorrection #(
reg signed [31:0] data_cal[3], data_cache[3];
wire signed [31:0] max, min, delta, value, light, saturation, alpha;
always @(posedge clk or posedge reset) begin
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
@@ -60,7 +60,7 @@ module SaturationCorrection #(
? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
: (saturation_inc);
always @(posedge clk or posedge reset) begin
always @(posedge clk) begin
if (reset) begin
out_en <= 0;
out_data[0] <= 0;
@@ -101,9 +101,9 @@ module SaturationCorrection #(
if (in_ready) begin
out_en <= 1;
if (enable && delta != 0) begin
out_data[0] <= (data_cal[0] <= 65535) ? (data_cal[0] > 0 ? data_cal[0][15:8] : 0) : 255;
out_data[1] <= (data_cal[1] <= 65535) ? (data_cal[1] > 1 ? data_cal[1][15:8] : 1) : 255;
out_data[2] <= (data_cal[2] <= 65535) ? (data_cal[2] > 2 ? data_cal[2][15:8] : 2) : 255;
out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
out_data[1] <= (|data_cal[1][31:16]) ? 255 : (data_cal[1] > 0 ? data_cal[1][15:8] : 0);
out_data[2] <= (|data_cal[2][31:16]) ? 255 : (data_cal[2] > 0 ? data_cal[2][15:8] : 0);
end else begin
out_data[0] <= data_cache[0][7:0];
out_data[1] <= data_cache[1][7:0];

116
Color/WhiteBalance.sv
View File

@@ -2,9 +2,11 @@
// 三通道图像合成一个RGB图像
module WhiteBalance #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
parameter reg [8:0] BUFF_SIZE = 32
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
parameter reg [8:0] BUFF_SIZE = 32,
parameter reg [31:0] RAM_BEGIN_ADDR = 0,
parameter reg [31:0] IM_SIZE = 1920 * 1080
) (
input wire clk,
input wire reset,
@@ -17,22 +19,116 @@ module WhiteBalance #(
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [OUT_DEPTH - 1:0] out_data[3],
output wire out_en,
output wire [OUT_DEPTH - 1:0] out_data[3],
input wire enable,
input wire [8:0] flame_rate
input wire [8:0] flame_rate,
input wire [31:0] white_gain[3]
);
assign out_ready = (!reset) ? 1 : 0;
assign out_receive = (in_en && !reset) ? 1 : 0;
wire ram_read_en, ram_write_en, ram_read_ready, ram_write_ready;
wire [31:0] ram_read_data, ram_read_addr, ram_write_data, ram_write_addr;
reg [8:0] cnt_flame;
reg [31:0] cnt_in_pic, cnt_out_pic, cnt_pixels;
reg [31:0] red_total, green_total, blue_total;
reg [31:0] r_white_gain[3];
wire is_finish_cal;
always @(*) begin
if (cnt_in_pic >= IM_SIZE) is_finish_cal = 1;
else if (cnt_out_pic >= IM_SIZE) is_finish_cal = 0;
else is_finish_cal = is_finish_cal;
end
assign ram_read_addr = cnt_out_pic;
assign ram_write_addr = cnt_in_pic;
assign cnt_pixels = (is_finish_cal)
? IM_SIZE - cnt_out_pic + cnt_in_pic
: cnt_in_pic - cnt_out_pic;
assign out_ready = (!in_en && !reset && cnt_pixels < IM_SIZE) ? 1 : 0;
assign out_receive = (in_en && !reset && cnt_in_pic < IM_SIZE) ? 1 : 0;
DiffWidthSyncFIFO #(
.DATA_WIDTH (8),
.DATA_DEPTH (12),
.READ_DEPTH (4),
.WRITE_DEPTH(3)
) in_fifo (
.clk(clk),
.reset(reset),
.read_ready(ram_write_ready),
.read_en(ram_write_en),
.read_data(ram_write_data),
.write_ready(in_ready),
.write_en(in_en),
.write_data(in_data)
);
)
DiffWidthSyncFIFO #(
.DATA_WIDTH (8),
.DATA_DEPTH (12),
.READ_DEPTH (3),
.WRITE_DEPTH(4)
) out_fifo (
.clk(clk),
.reset(reset),
.read_ready(out_ready),
.read_en(out_en),
.read_data(out_data),
.write_ready(ram_read_ready),
.write_en(ram_read_en),
.write_data(ram_read_data)
);
SDRAM inst_RAM (
.clk(clk),
.read_en(ram_read_en),
.read_addr(ram_read_addr),
.read_data(ram_read_data),
.read_ready(ram_read_ready),
.write_en(ram_write_en),
.write_addr(ram_write_addr),
.write_data(ram_write_data),
.write_ready(ram_write_ready)
);
// calculate white gain
always @(posedge clk) begin
if(reset) begin
if (reset) begin
red_total <= 0;
green_total <= 0;
blue_total <= 0;
cnt_flame <= 0;
cnt_in_pic <= 0;
r_white_gain[0] <= white_gain[0];
r_white_gain[1] <= white_gain[1];
r_white_gain[2] <= white_gain[2];
end else begin
if (in_en && cnt_pixels < IM_SIZE) begin
red_total <= red_total + in_data[0];
green_total <= green_total + in_data[1];
blue_total <= blue_total + in_data[2];
if (cnt_in_pic < IM_SIZE) cnt_in_pic <= cnt_in_pic + 1;
else cnt_in_pic <= 0;
end else begin
end
end
end
// calculate out data
always @(posedge clk) begin
if (reset) begin
cnt_out_pic <= 0;
end else begin
if (out_ready && is_finish_cal) begin
out_en <= 1;
end else begin
out_en <= 0;
end
end
end