36 lines
719 B
Systemverilog
36 lines
719 B
Systemverilog
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//Gowin SDPB IP<49>˷<EFBFBD><CBB7><EFBFBD><EFBFBD>ļ<EFBFBD>
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`timescale 1ns / 1ps
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module Gowin_SDPB (
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input wire clka,
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input wire clkb, //no use
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input wire reset,
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input wire cea,
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input wire ceb,
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input wire [10:0] ada,
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input wire [10:0] adb,
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input wire [15:0] din,
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output reg [15:0] dout,
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input wire oce //no use
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);
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reg [15:0] bram[2048];
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integer i;
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initial for (i = 0; i < 2048; i = i + 1) bram[i] = 0;
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always @(posedge clka) begin
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if (reset) for (i = 0; i < 2048; i = i + 1) bram[i] <= 0;
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else if (cea) bram[ada] <= din;
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end
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always @(posedge clka) begin
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if (reset) dout <= 0;
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else if (ceb) dout <= bram[adb];
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end
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endmodule
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