57 lines
2.0 KiB
Systemverilog
57 lines
2.0 KiB
Systemverilog
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`timescale 1ns / 1ps
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module Windows #(
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parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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)(
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// 基本信号
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input wire clk,
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input wire reset,
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// 数据线
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input wire [DATA_WIDTH - 1:0] in_data [3], // 0、1、2分别表示第一、二、三行
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output reg [DATA_WIDTH - 1:0] out_data [3*3], // 数据输出线
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// 有效信号
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input wire in_valid, // 上一模块输出数据有效
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output wire out_valid, // 当前模块输出数据有效
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// 准备信号
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input wire in_ready, // 下一模块可接受新数据
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output wire out_ready // 当前模块可接收新数据
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);
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localparam PIPILINE = 3;
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reg [PIPILINE-1:0] pipeline_valid;
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = (pipeline_valid != {PIPILINE{1'b1}}) | ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready);
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = (pipeline_valid == {PIPILINE{1'b1}});
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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for(i=0;i<9;i=i+1) out_data[i] <= 0;
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pipeline_valid <= 0;
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end else begin
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if((pipeline_valid != {PIPILINE{1'b1}}) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
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pipeline_valid[0] <= in_valid;
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out_data[6] <= in_data[0];
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out_data[7] <= in_data[1];
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out_data[8] <= in_data[2];
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end
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if((pipeline_valid[2] == 0) || (pipeline_valid[1] == 0) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
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pipeline_valid[1] <= pipeline_valid[0];
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out_data[3] <= out_data[6];
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out_data[4] <= out_data[7];
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out_data[5] <= out_data[8];
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end
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if((pipeline_valid[2] == 0) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
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pipeline_valid[2] <= pipeline_valid[1];
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out_data[0] <= out_data[3];
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out_data[1] <= out_data[4];
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out_data[2] <= out_data[5];
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end
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end
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end
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endmodule
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