ISP/Merge/chanels_to_RGB.v

`timescale 1ns/1ps

// 三通道图像合成一个RGB图像
module chanels_to_RGB #(
    parameter IN_DEPTH = 12,        // 输入图像的色深
    parameter OUT_DEPTH = 8         // 输出图像的色深
) (
    input clk,
    input reset,

    input in_en,
    input [15:0] data_in [2:0], // 0:R 1:G 2:B

    // 输出相关
    input out_que,                                 // 数据请求
    output out_en,
    output [3 * OUT_DEPTH - 1:0] data_out
);
    localparam READ_DATA = 0;
    localparam SEND_DATA = 1;

    reg [1:0] state, nextState;
    reg [31:0] data_cal [2:0]; // 用于保存运算结果，防止溢出
    reg fifo_en;
    reg [3 * OUT_DEPTH - 1:0] fifo_in; // 输入fifo中缓存
    wire fifo_empty, fifo_que;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= READ_DATA;
        end
        else begin
            state <= nextState;
        end
    end

    always @(*) begin
        case (state)
            READ_DATA: nextState = (in_en) ? SEND_DATA : READ_DATA;
            SEND_DATA: nextState = READ_DATA;
        endcase
    end

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            // 初始化
            data_cal[0] <= 0;
            data_cal[1] <= 0;
            data_cal[2] <= 0;
            fifo_en <= 0;
            fifo_in <= 0;
        end
        else begin
            case (state)
                READ_DATA: begin
                    fifo_en <= 0;

                    if (in_en) begin
                        data_cal[0] <= data_in[0] * OUT_DEPTH / IN_DEPTH;
                        data_cal[1] <= data_in[1] * OUT_DEPTH / IN_DEPTH;
                        data_cal[2] <= data_in[2] * OUT_DEPTH / IN_DEPTH;

                    end
                end 

                SEND_DATA: begin
                    fifo_en <= 1;
                    fifo_in <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0], data_cal[2][OUT_DEPTH - 1:0]};
                end
            endcase
        end
    end

    // 存在数据请求且FIFO不为空时，才发送数据
    assign fifo_que = (out_que && !fifo_empty) ? 1 : 0;

    SOFTFIFO #(
        .DATA_WIDTH_W(3 * OUT_DEPTH),
        .DATA_WIDTH_R(3 * OUT_DEPTH)
    ) RGB_FIFO (
    .rst(reset),  //asynchronous port,active hight
    .clkw(clk),  //write clock
    .clkr(clk),  //read clock
    .we(fifo_en),  //write enable,active hight
    .di(fifo_in),  //write data
    .re(fifo_que),  //read enable,active hight
    .dout(data_out),  //read data
    .valid(out_en),  //read data valid flag
    /* verilator lint_off PINCONNECTEMPTY */
    .full_flag(),  //fifo full flag
    .empty_flag(fifo_empty),  //fifo empty flag
    /* verilator lint_off PINCONNECTEMPTY */
    .afull(),  //fifo almost full flag
    /* verilator lint_off PINCONNECTEMPTY */
    .aempty(),  //fifo almost empty flag
    /* verilator lint_off PINCONNECTEMPTY */
    .wrusedw(),  //stored data number in fifo
    /* verilator lint_off PINCONNECTEMPTY */
    .rdusedw() //available data number for read 
    );

endmodule