mirror of
https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-13 04:25:32 +08:00
SikongJueluo
2da17e101b
BREAKING CHANGE: CAM write and query interface replaced with standard valid/ready handshake. wr_en/wr_row/wr_hash → wr_valid/wr_ready/wr_addr/write_hash. External noise_mask_lanes_flat removed; noise generation now handled internally by cam_noisy module with configurable rate via parameters. - cam_top: add parameters (NOISE_EN, NOISE_RATE_NUM/DEN, NOISE_GEN/SAMPLE_BITS, NOISE_SEED) - cam_top: replace cam_core with cam_noisy (integrated noise generation) - match_engine: remove external noise_mask_lanes_flat input - hw/sim: update Makefile with noise parameters and compile args - hw/sim/model: add generate_write_flip_mask() and xorshift64() matching RTL behavior - hw/sim/tests: adapt testbench to new handshake protocol
99 lines
3.4 KiB
Systemverilog
99 lines
3.4 KiB
Systemverilog
`timescale 1ns/1ps
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`include "cam_params.svh"
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module cam_top #(
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parameter bit NOISE_EN = 1'b1,
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parameter int NOISE_RATE_NUM = 1,
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parameter int NOISE_RATE_DEN = 100,
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parameter int NOISE_GEN_BITS = 8,
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parameter int NOISE_SAMPLE_BITS = 8,
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parameter logic [63:0] NOISE_SEED = 64'hB504_F32D_B504_F32D
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) (
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input logic clk,
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input logic rst_n,
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// Write interface (handshake)
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_addr,
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input logic [(`HASH_BITS)-1:0] write_hash,
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// Query interface
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input logic query_valid,
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output logic query_ready,
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input logic [(`HASH_BITS)-1:0] query_hash,
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// Result interface
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output logic result_valid,
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input logic result_ready,
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output logic [(`ROW_BITS)-1:0] top1_index,
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output logic [(`SCORE_BITS)-1:0] top1_score,
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`ifdef SIM_DEBUG
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output logic [(`NUM_ROWS)*(`SCORE_BITS)-1:0] score_debug_flat,
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`endif
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output logic busy
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);
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// ── Internal signals ──
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logic storage_wr_ready; // cam_noisy idle
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logic match_query_ready; // match_engine idle
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logic match_busy; // match_engine scanning/result pending
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// ── Internal valid forwarding ──
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logic storage_wr_valid;
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logic match_query_valid;
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// ── Half-duplex arbitration (write-priority) ──
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// When both wr_valid and query_valid are high, write wins.
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assign wr_ready = storage_wr_ready && match_query_ready;
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assign query_ready = storage_wr_ready && match_query_ready && !wr_valid;
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assign busy = (!storage_wr_ready) || match_busy || (!match_query_ready);
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// ── Internal valid forwarding (only assert to sub-modules when top-level accepts) ──
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assign storage_wr_valid = wr_valid && wr_ready;
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assign match_query_valid = query_valid && query_ready;
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// ── Shared read bus ──
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wire [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat;
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wire [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat;
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cam_noisy #(
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.NOISE_EN (NOISE_EN),
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.NOISE_RATE_NUM (NOISE_RATE_NUM),
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.NOISE_RATE_DEN (NOISE_RATE_DEN),
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.NOISE_GEN_BITS (NOISE_GEN_BITS),
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.NOISE_SAMPLE_BITS (NOISE_SAMPLE_BITS),
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.NOISE_SEED (NOISE_SEED)
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) u_noisy (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (storage_wr_valid),
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.wr_ready (storage_wr_ready),
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.wr_addr (wr_addr),
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.write_hash (write_hash),
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.rd_addr_lanes_flat (rd_addr_lanes_flat),
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.rd_hash_lanes_flat (rd_hash_lanes_flat)
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);
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match_engine u_match (
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.clk (clk),
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.rst_n (rst_n),
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.query_valid (match_query_valid),
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.query_ready (match_query_ready),
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.query_hash (query_hash),
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.result_valid (result_valid),
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.result_ready (result_ready),
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.result_row (top1_index),
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.result_score (top1_score),
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.busy (match_busy),
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.rd_addr_lanes_flat (rd_addr_lanes_flat),
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.rd_hash_lanes_flat (rd_hash_lanes_flat)
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`ifdef SIM_DEBUG
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,.score_debug_flat (score_debug_flat)
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`endif
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);
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endmodule
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