build(simulation): improve verilator simulation infrastructure

- Add verilator to dependencies
- Add configurable logging via QUIET/VERBOSE/COCOTB_LOG_LEVEL env vars
- Add optional warning suppression (SUPPRESS_VERILATOR_WARNINGS)
- Clean up and restructure Makefile

hw/sim/Makefile

@@ -1,14 +1,9 @@
-# Minimal cocotb Makefile.
-# Examples:
-#   make TESTCASE=basic_write_query_no_noise
-#   make TESTCASE=external_noise_mask EXTRA_DEFINES="+define+SIM_NOISE +define+SIM_DEBUG"
-#
-# Verilator is preferred. Icarus may not support all SystemVerilog constructs used here.
-
 SIM ?= verilator
 TOPLEVEL_LANG ?= verilog
 TOPLEVEL := cam_top
-MODULE ?= tests.test_cam_basic
+
+# MODULE ?= tests.test_cam_basic
+COCOTB_TEST_MODULES ?= tests.test_cam_basic
 
 NUM_ROWS ?= 512
 HASH_BITS ?= 512
@@ -16,16 +11,26 @@ LANES ?= 16
 
 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
 
-# cocotb passes PLUSARGS/EXTRA_ARGS differently across simulators. Keep
-# SystemVerilog parameters explicit through COMPILE_ARGS for Verilator.
 COMPILE_ARGS += -Wall -Wno-fatal
 COMPILE_ARGS += -I$(PWD)/../rtl
 COMPILE_ARGS += +define+SIM_DEBUG
 COMPILE_ARGS += $(EXTRA_DEFINES)
 
+# Cleaner terminal output
+export QUIET ?= 1
+export VERBOSE ?= 0
+export COCOTB_LOG_LEVEL ?= INFO
+export PYTHONWARNINGS ?= ignore::pytest.PytestDeprecationWarning
+
+# Optional temporary suppression
+SUPPRESS_VERILATOR_WARNINGS ?= 0
+ifeq ($(SUPPRESS_VERILATOR_WARNINGS),1)
+COMPILE_ARGS += -Wno-WIDTHEXPAND
+COMPILE_ARGS += -Wno-UNOPTFLAT
+endif
+
 VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
 VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
-
 VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
 VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv