diff --git a/.editorconfig b/.editorconfig
new file mode 100644
index 0000000..e62b828
--- /dev/null
+++ b/.editorconfig
@@ -0,0 +1,6 @@
+root = true
+
+[*]
+end_of_line = lf
+insert_final_newline = true
+charset = utf-8
diff --git a/.gitignore b/.gitignore
index a310763..9fb7057 100644
--- a/.gitignore
+++ b/.gitignore
@@ -136,6 +136,7 @@ celerybeat.pid
 
 # Environments
 .env
+.env.remote
 .venv
 env/
 venv/
diff --git a/.rsyncignore b/.rsyncignore
index 43bc047..4d0c1a6 100644
--- a/.rsyncignore
+++ b/.rsyncignore
@@ -1,12 +1,15 @@
-.jj/
-.git/
-.devenv/
-.direnv/
-deps/
-outputs/
-data/versioned_data/
-datasets/
-.ruff_cache/
-.pytest_cache/
-.sisyphus/
-.logs/
+.jj
+.git
+.devenv
+.direnv
+deps
+outputs
+data/versioned_data
+datasets
+.ruff_cache
+.pytest_cache
+.sisyphus
+.logs
+.opencode
+.venv
+**/__pycache__
diff --git a/environment.yml b/environment.yml
index 70715bd..4e3b2e6 100644
--- a/environment.yml
+++ b/environment.yml
@@ -16,5 +16,6 @@ dependencies:
   - pytorch-cuda=12.1
   # Toolsets
   - uv
+  - verilator
   - just
   - nodejs>=20.0.0
diff --git a/hw/sim/Makefile b/hw/sim/Makefile
index 49fcbe2..a0a74a6 100644
--- a/hw/sim/Makefile
+++ b/hw/sim/Makefile
@@ -1,14 +1,9 @@
-# Minimal cocotb Makefile.
-# Examples:
-#   make TESTCASE=basic_write_query_no_noise
-#   make TESTCASE=external_noise_mask EXTRA_DEFINES="+define+SIM_NOISE +define+SIM_DEBUG"
-#
-# Verilator is preferred. Icarus may not support all SystemVerilog constructs used here.
-
 SIM ?= verilator
 TOPLEVEL_LANG ?= verilog
 TOPLEVEL := cam_top
-MODULE ?= tests.test_cam_basic
+
+# MODULE ?= tests.test_cam_basic
+COCOTB_TEST_MODULES ?= tests.test_cam_basic
 
 NUM_ROWS ?= 512
 HASH_BITS ?= 512
@@ -16,16 +11,26 @@ LANES ?= 16
 
 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
 
-# cocotb passes PLUSARGS/EXTRA_ARGS differently across simulators. Keep
-# SystemVerilog parameters explicit through COMPILE_ARGS for Verilator.
 COMPILE_ARGS += -Wall -Wno-fatal
 COMPILE_ARGS += -I$(PWD)/../rtl
 COMPILE_ARGS += +define+SIM_DEBUG
 COMPILE_ARGS += $(EXTRA_DEFINES)
 
+# Cleaner terminal output
+export QUIET ?= 1
+export VERBOSE ?= 0
+export COCOTB_LOG_LEVEL ?= INFO
+export PYTHONWARNINGS ?= ignore::pytest.PytestDeprecationWarning
+
+# Optional temporary suppression
+SUPPRESS_VERILATOR_WARNINGS ?= 0
+ifeq ($(SUPPRESS_VERILATOR_WARNINGS),1)
+COMPILE_ARGS += -Wno-WIDTHEXPAND
+COMPILE_ARGS += -Wno-UNOPTFLAT
+endif
+
 VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
 VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
-
 VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
 VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv