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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
8b8e4d3118
- Add verilator to dependencies - Add configurable logging via QUIET/VERBOSE/COCOTB_LOG_LEVEL env vars - Add optional warning suppression (SUPPRESS_VERILATOR_WARNINGS) - Clean up and restructure Makefile
39 lines
1.0 KiB
Makefile
39 lines
1.0 KiB
Makefile
SIM ?= verilator
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TOPLEVEL_LANG ?= verilog
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TOPLEVEL := cam_top
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# MODULE ?= tests.test_cam_basic
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COCOTB_TEST_MODULES ?= tests.test_cam_basic
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NUM_ROWS ?= 512
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HASH_BITS ?= 512
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LANES ?= 16
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EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
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COMPILE_ARGS += -Wall -Wno-fatal
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COMPILE_ARGS += -I$(PWD)/../rtl
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COMPILE_ARGS += +define+SIM_DEBUG
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COMPILE_ARGS += $(EXTRA_DEFINES)
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# Cleaner terminal output
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export QUIET ?= 1
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export VERBOSE ?= 0
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export COCOTB_LOG_LEVEL ?= INFO
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export PYTHONWARNINGS ?= ignore::pytest.PytestDeprecationWarning
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# Optional temporary suppression
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SUPPRESS_VERILATOR_WARNINGS ?= 0
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ifeq ($(SUPPRESS_VERILATOR_WARNINGS),1)
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COMPILE_ARGS += -Wno-WIDTHEXPAND
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COMPILE_ARGS += -Wno-UNOPTFLAT
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endif
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VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
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VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
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VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
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VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
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VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv
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include $(shell uv run cocotb-config --makefiles)/Makefile.sim
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