mirror of
https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
SikongJueluo
f5daaa2667
- Split cam_core into pure memory (cam_core.sv) and match engine (match_engine.sv) - Add cam_params.svh with centralized parameter definitions (NUM_ROWS, HASH_BITS, LANES, etc.) - Update cam_top.sv to use shared parameters and compose match_engine - Update Makefile to include new match_engine module and correct Verilator define syntax
34 lines
1.1 KiB
Makefile
34 lines
1.1 KiB
Makefile
# Minimal cocotb Makefile.
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# Examples:
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# make TESTCASE=basic_write_query_no_noise
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# make TESTCASE=external_noise_mask EXTRA_DEFINES="+define+SIM_NOISE +define+SIM_DEBUG"
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#
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# Verilator is preferred. Icarus may not support all SystemVerilog constructs used here.
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SIM ?= verilator
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TOPLEVEL_LANG ?= verilog
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TOPLEVEL := cam_top
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MODULE ?= tests.test_cam_basic
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NUM_ROWS ?= 512
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HASH_BITS ?= 512
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LANES ?= 16
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EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
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# cocotb passes PLUSARGS/EXTRA_ARGS differently across simulators. Keep
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# SystemVerilog parameters explicit through COMPILE_ARGS for Verilator.
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COMPILE_ARGS += -Wall -Wno-fatal
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COMPILE_ARGS += -I$(PWD)/../rtl
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COMPILE_ARGS += +define+SIM_DEBUG
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COMPILE_ARGS += $(EXTRA_DEFINES)
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VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
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VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
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VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
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VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv
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VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv
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include $(shell uv run cocotb-config --makefiles)/Makefile.sim
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