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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
8b4d4c1b57
- Make cam_read_noise a pass-through module, removing all noise injection logic - Switch write noise to use noise_mask_bernoulli instead of noise_mask_grouped - Add state machine to cam_write_noise for mask generation timing - Remove noise_mask_grouped.sv (no longer needed) - Remove read noise parameters from cam_noisy and cam_top - Update simulation and benchmark code to reflect read noise removal - Sync documentation to reflect Phase 2 architecture
42 lines
1.6 KiB
Plaintext
42 lines
1.6 KiB
Plaintext
# synth_cam_top_flat.ys — Flattened CAM top synthesis for Xilinx Zynq-7020 / 7-series
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# Run from hw/syn: yosys -s synth_cam_top_flat.ys
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# Set include directories before reading RTL
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verilog_defaults -push
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verilog_defaults -add -I../rtl
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verilog_defaults -add -I../rtl/core
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verilog_defaults -add -I../rtl/noise
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verilog_defaults -add -I../rtl/random
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# Read RTL sources in canonical order
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read_verilog -sv -D SYNTHESIS ../rtl/random/random128.sv
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read_verilog -sv -D SYNTHESIS ../rtl/noise/noise_mask_bernoulli.sv
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read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
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read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/candidate_fifo.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/topk_tracker.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/result_serializer.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
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read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
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read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv
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# Restore verilog defaults
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verilog_defaults -pop
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# Flattened Xilinx synthesis (includes proc, opt, fsm, memory, etc.)
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synth_xilinx -family xc7 -top cam_top -flatten
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# Ensure build directory exists for output files
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exec -- mkdir -p build
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# Write flattened Verilog netlist
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write_verilog -attr2comment build/cam_top_synth.v
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# Resource statistics (JSON to file via tee, not mixed into logs)
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tee -q -o build/cam_top_flat_resources.json stat -tech xilinx -json
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# Final checks
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check -noinit
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